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? 2011-2012 microchip technology inc. preliminary ds61168d-page 1 pic32mx1xx/2xx operating conditions ? 2.3v to 3.6v, -40oc to +105oc, dc to 40 mhz core: 40 mhz mips32 ? m4k ? ? mips16e ? mode for up to 40% smaller code size ? 1.56 dmips/mhz (dhrystone 2.1) performance ? code-efficient (c and assembly) architecture ? single-cycle (mac) 32x16 and two-cycle 32x32 multiply clock management ? 0.9% internal oscillator ? programmable plls and oscillator clock sources ? fail-safe clock monitor (fscm) ? independent watchdog timer ? fast wake-up and start-up power management ? low-power management modes (sleep, idle) ? integrated power-on reset and brown-out reset ? 0.5 ma/mhz dynamic current (typical) ?20 a i pd current (typical) audio interface features ? data communication: i 2 s, lj, rj, dsp modes ? control interface: spi and i 2 c? ? master clock: - generation of fractional clock frequencies - can be synchronized with usb clock - can be tuned in run-time advanced analog features ? adc module: - 10-bit 1.1 msps rate with one s&h - up to 10 analog inputs on 28-pin devices and 13 analog inputs on 44-pin devices ? flexible and independent adc trigger sources ? charge time measurement unit (ctmu): - supports mtouch? capacitive touch sensing - provides high-resolution time measurement (1 ns) - on-chip temperature measurement capability ? comparators: - up to three analog comparator modules - programmable references with 32 voltage points timers/output compare/input capture ? five general purpose timers: - five 16-bit and up to two 32-bit timers/counters ? five output compare (oc) modules ? five input capture (ic) modules ? peripheral pin select (pps) to allow function remap ? real-time clock and calendar (rtcc) module communication interfaces ? usb 2.0-compliant full-speed otg controller ? two uart modules (10 mbps) - supports lin 2.0 protocols and irda ? support ? two 4-wire spi modules (20 mbps) ?two i 2 c modules (up to 1 mbaud) with smbus support ? peripheral pin select (pps) to allow function remap ? parallel master port (pmp) direct memory access (dma) ? four channels of hardware dma with automatic data size detection ? two additional channels dedicated for usb ? programmable cyclic redundancy check (crc) input/output ? 15 ma source/sink on all i/o pins ? 5v-tolerant pins ? selectable open drain, pull-ups, and pull-downs ? external interrupts on all i/o pins qualification and class b support ? aec-q100 revg (grade 2 -40oc to +105oc) planned ? class b safety library, iec 60730 debugger development support ? in-circuit and in-application programming ?4-wire mips ? enhanced jtag interface ? unlimited program and six complex data breakpoints ? ieee 1149.2-compatible (jtag) boundary scan packages type soic ssop spdip qfn vtla tqfp pin count 28 28 28 28 44 36 44 44 i/o pins (up to) 21 21 21 21 34 25 34 34 contact/lead pitch 1.27 0.65 0.100'' 0.65 0.65 0.50 0.50 0.80 dimensions 17.90x7.50x2.65 10.2x5.3x2 1. 365x.285x.135'' 6x6x0.9 8x8x0.9 5x5x0.9 6x6x0.9 10x10x1 note: all dimensions are in millimeters (mm) unless specified. 32-bit microcontrollers (up to 128 kb flash and 32 kb sram) with audio and graphics interfaces , usb, and advanced analog www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 2 preliminary ? 2011-2012 microchip technology inc. table 1: pic32mx1xx general purpose family features device pins program memory (kb) (1) data memory (kb) remappable peripherals analog comparators usb on-the-go (otg) i 2 c? pmp dma channels (programmable/dedicated) ctmu 10-bit 1 msps adc (channels) rtcc i/o pins jtag packages remappable pins timers (2) /capture/compare uart spi/i 2 s external interrupts (3) PIC32MX110F016B 28 16+3 4 20 5/5/5 2253n2y4/0y10y21y soic, ssop, spdip, qfn pic32mx110f016c 36 16+3 4 24 5/5/5 2253n2y4/0y12y25yvtla pic32mx110f016d 44 16+3 4 32 5/5/5 2253n2y4/0y13y34y vtla, tqfp, qfn pic32mx120f032b 28 32+3 8 20 5/5/5 2253n2y4/0y10y21y soic, ssop, spdip, qfn pic32mx120f032c 36 32+3 8 24 5/5/5 2253n2y4/0y12y25yvtla pic32mx120f032d 44 32+3 8 32 5/5/5 2253n2y4/0y13y34y vtla, tqfp, qfn pic32mx130f064b 28 64+3 16 20 5/5/5 2253n2y4/0y10y21y soic, ssop, spdip, qfn pic32mx130f064c 36 64+3 16 24 5/5/5 2253n2y4/0y12y25yvtla pic32mx130f064d 44 64+3 16 32 5/5/5 2253n2y4/0y13y34y vtla, tqfp, qfn pic32mx150f128b 28 128+3 32 20 5/5/5 2253n2y4/0y10y21y soic, ssop, spdip, qfn pic32mx150f128c 36 128+3 32 24 5/5/5 2253n2y4/0y12y25yvtla pic32mx150f128d 44 128+3 32 32 5/5/5 2253n2y4/0y13y34y vtla, tqfp, qfn note 1: this device features 3 kb of boot flash memory. 2: four out of five timers are remappable. 3: four out of five external interrupts are remappable. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 3 pic32mx1xx/2xx table 2: pic32mx2xx usb family features device pins program memory (kb) (1) data memory (kb) remappable peripherals analog comparators usb on-the-go (otg) i 2 c? pmp dma channels (programmable/dedicated) ctmu 10-bit 1 msps adc (channels) rtcc i/o pins jtag packages remappable pins timers (2) /capture/compare uart spi/i 2 s external interrupts (3) pic32mx210f016b 28 16+3 4 19 5/5/5 2253y2y4/2y9y19y soic, ssop, spdip, qfn pic32mx210f016c 36 16+3 4 23 5/5/5 2253y2y4/2y12y23yvtla pic32mx210f016d 44 16+3 4 31 5/5/5 2253y2y4/2y13y33y vtla, tqfp, qfn pic32mx220f032b 28 32+3 8 19 5/5/5 2253y2y4/2y9y19y soic, ssop, spdip, qfn pic32mx220f032c 36 32+3 8 23 5/5/5 2253y2y4/2y12y23yvtla pic32mx220f032d 44 32+3 8 31 5/5/5 2253y2y4/2y13y33y vtla, tqfp, qfn pic32mx230f064b 28 64+3 16 19 5/5/52253y2y4/2y9y19y soic, ssop, spdip, qfn pic32mx230f064c 36 64+3 16 23 5/5/52253y2y4/2y12y23yvtla pic32mx230f064d 44 64+3 16 31 5/5/52253y2y4/2y13y33y vtla, tqfp, qfn pic32mx250f128b 28 128+3 32 19 5/5/52253y2y4/2y9y19y soic, ssop, spdip, qfn pic32mx250f128c 36 128+3 32 23 5/5/52253y2y4/2y12y23yvtla pic32mx250f128d 44 128+3 32 31 5/5/52253y2y4/2y13y33y vtla, tqfp, qfn note 1: this device features 3 kb of boot flash memory. 2: four out of five timers are remappable. 3: four out of five external interrupts are remappable. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 4 preliminary ? 2011-2012 microchip technology inc. pin diagrams note 1: the rpn pins can be used by remappable peripherals. see tab l e 1 for the available peripherals and section 11.3 ?peripheral pin select? for restrictions. 2: every i/o port pin (rax-rcx) can be used as a change notification pin (cnax-cncx). see section 11.0 ?i/o ports? for more information. mclr v ref +/cv ref +/an0/c3inc/rpa0/cted1/ra0 v ref -/cv ref -/an1/rpa1/cted2/ra1 an9/c3ina/rpb15/sck2/cted6/pmcs1/rb15 pged1/an2/c1ind/c2inb/c3ind/rpb0/rb0 cv ref /an10/c3inb/rpb14/sck1/cted5/pmwr/rb14 pgec1/an3/c1inc/c2ina/rpb1/cted 12/rb1 an11/rpb13/ctpls/pmrd/rb13 an4/c1inb/c2ind/rp b2/sda2/cted13/rb2 an12/pmd0/rb12 pgec2/tms/rpb11/pmd1/rb11 v ss pged2/rpb10/cted11/pmd2/rb10 osc1/clki/rpa2/ra2 osc2/clko/rpa3/pma0/ra3 v ss sosci/rpb4/rb4 tdo/rpb9/sda1/cted4/pmd3/rb9 sosco/rpa4/t1ck/cted9/pma1/ra4 tck/rpb8/scl1/cted10/pmd4/rb8 v dd tdi/rpb7/cted3/pmd5/int0/rb7 pgec3/rpb6/pmd6/rb6 mclr av dd av ss an5/c1ina/c2inc/rtcc/rpb3/scl2/rb3 v ss v ss sosco/rpa4/t1ck/cted9/pma1/ra4 v dd mclr v ss v ss sosco/rpa4/t1ck/cted9/pma1/ra4 v dd 28-pin soic, spdip, ssop (1,2) = pins are up to 5v tolerant mclr v ss v cap v ss sosco/rpa4/t1ck/cted9/pma1/ra4 v dd pged3/rpb5/pmd7/rb5 mclr 128av dd pged3/v ref +/cv ref +/an0/c3inc/rpa0/cted1/pmd7/ra0 227av ss pgec3/v ref -/cv ref -/an1/rpa1/cted2/pmd6/ra1 3 26 an9/c3ina/rpb15/sck2/cted6/pmcs1/rb15 pged1/an2/c1ind/c2inb/c3 ind/rpb0/pmd0/rb0 4 25 cv ref /an10/c3inb/rpb14/vbuson/sck1/cted5/rb14 pgec1/an3/c1inc/c2ina/rpb1/cted12/pmd1/rb1 5 24 an11/rpb13/ctpls/pmrd/rb13 an4/c1inb/c2ind/rpb2/s da2/cted13/pmd2/rb2 6 23 v usb 3 v 3 an5/c1ina/c2inc/rtcc/rpb3/scl2/pmwr/rb3 7 22 pgec2/rpb11/d-/rb11 v ss 8 21 pged2/rpb10/d+/cted11/rb10 osc1/clki/rpa2/ra2 9 20 v cap osc2/clko/rpa3/pma0/ra3 10 19 v ss sosci/rpb4/rb4 11 18 tdo/rpb9/sda1/cted4/pmd3/rb9 sosco/rpa4/t1ck/cted9/pma1/ra4 12 17 tck/rpb8/scl1/cted10/pmd4/rb8 v dd 13 16 tdi/rpb7/cted3/pmd5/int0/rb7 tms/rpb5/usbid/rb5 14 15 v bus pic32mx210f016b pic32mx220f032b 128 227 326 425 524 623 722 821 920 10 19 11 18 12 17 13 16 14 15 PIC32MX110F016B pic32mx120f032b pic32mx130f064b pic32mx150f128b pic32mx230f064b pic32mx250f128b www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 5 pic32mx1xx/2xx pin diagrams (continued) 28-pin qfn (1,2,3) = pins are up to 5v tolerant note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 11.3 ?peripheral pin select? for restrictions. 2: every i/o port pin (rax-rcx) can be used as a change notification pin (cnax-cncx). see section 11.0 ?i/o ports? for more information. 3: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. v ref -/cv ref -/an1/rpa1/cted2/ra1 v ref +/cv ref +/an0/c3inc/rpa0/cted1/ra0 mclr av dd av ss an9/c3ina/rpb15/sck2/cted6/pmcs1/rb15 cv ref /an10/c3inb/rpb14/sck1/cted5/pmwr/rb14 28 27 26 25 24 23 22 pged1/an2/c1ind/c2inb/c3ind/rpb0/rb0 121 an11/rpb13/ctpls/pmrd/rb13 pgec1/an3/c1inc/c2ina/rpb1/cted12/rb1 220 an12/pmd0/rb12 an4/c1inb/c2ind/rp b2/sda2/cted13/rb2 319 pgec2/tms/rpb11/pmd1/rb11 an5/c1ina/c2inc/rt cc/rpb3/scl2/rb3 4 PIC32MX110F016B 18 pged2/rpb10/cted11/pmd2/rb10 v ss 517 v cap osc1/clki/rpa2/ra2 616 v ss osc2/clko/rpa3/pma0/ra3 715 tdo/rpb9/sda1/cted4/pmd3/rb9 8 9 10 11 12 13 14 sosci/rpb4/rb4 sosco/rpa4/t1ck/cted9/pma1/ra4 v dd pged3/rpb5/pmd7/rb5 pgec3/rpb6/pmd6/rb6 tdi/rpb7/cted3/pmd5/int0/rb7 tck/rpb8/scl1/cted10/pmd4/rb8 pic32mx120f032b pic32mx130f064b pic32mx150f128b www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 6 preliminary ? 2011-2012 microchip technology inc. pin diagrams (continued) 28-pin qfn (1,2,3) = pins are up to 5v tolerant pgec3/v ref -/cv ref -/an1/rpa1/cted2/pmd6/ra1 pged3/v ref +/cv ref +/an0/c3inc/rpa0 /cted1/pmd7/ra0 mclr av dd av ss an9/c3ina/rpb15/sck2/cted6/pmcs1/rb15 cv ref /an10/c3inb/rpb14/vbu son/sck1/cted5/rb14 28 27 26 25 24 23 22 pged1/an2/c1ind/c2inb/ c3ind/rpb0/pmd0/rb0 121 an11/rpb13/ctpls/pmrd/rb13 pgec1/an3/c1inc/c2ina/rpb1/cted12/pmd1/rb1 220 v usb 3 v 3 an4/c1inb/c2ind/rpb2/sda2/cted13/pmd2/rb2 319 pgec2/rpb11/d-/rb11 an5/c1ina/c2inc/rtcc/ rpb3/scl2/pmwr/rb3 4 pic32mx210f016b 18 pged2/rpb10/d+/cted11/rb10 v ss 517 v cap osc1/clki/rpa2/ra2 616 v ss osc2/clko/rpa3/pma0/ra3 715 tdo/rpb9/sda1/cted4/pmd3/rb9 8 9 10 11 12 13 14 sosci/rpb4/rb4 sosco/rpa4/t1ck/cted9/pma1/ra4 v dd tms/rpb5/usbid/rb5 v bus tdi/rpb7/cted3/pmd5/int0/rb7 tck/rpb8/scl1/cted10/pmd4/rb8 pic32mx220f032b note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 11.3 ?peripheral pin select? for restrictions. 2: every i/o port pin (rax-rcx) can be used as a change notification pin (cnax-cncx). see section 11.0 ?i/o ports? for more information. 3: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. pic32mx230f064b pic32mx250f128b www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 7 pic32mx1xx/2xx pin diagrams (continued) 36-pin vtla (1,2,3) = pins are up to 5v tolerant note 1: the rpn pins can be used by remappable peripherals. see tab l e 1 for the available peripherals and section 11.3 ?peripheral pin select? for restrictions. 2: every i/o port pin (rax-rcx) can be used as a change notification pin (cnax-cncx). see section 11.0 ?i/o ports? for more information. 3: the metal plane at the bottom of the device is not co nnected to any pins and is recommended to be connected to v ss externally. 4: this pin function is available on pic32mx130f064c and pic32mx150f128c devices only. pic32mx120f032c 1 pic32mx110f016c 10 33 32 31 30 29 28 2 3 4 5 6 24 23 22 21 20 19 11 12 13 14 15 7 8 9 34 35 36 16 17 18 27 26 25 pgec1/an3/c1inc/c2ina/rpb1/cted12/rb1 pged1/an2/c1ind/c2inb/c3ind/rpb0/rb0 v ref -/cv ref -/an1/rpa1/cted2/ra1 v ref +/cv ref +/an0/c3inc/rpa0/cted1/ra0 mclr av dd av ss an9/c3ina/rpb15/sck2/cted6/pmcs1/rb15 cv ref /an10/c3inb/rpb14/sck1/cted5/pmwr/rb14 an4/c1inb/c2ind/rpb2/sda2/cted13/rb2 an11/rpb13/ctpls/pmrd/rb13 an5/c1ina/c2inc/rtcc/rpb3/scl2/rb3 an12/pmd0/rb12 pged (4) /an6/rpc0/rc0 pgec2/tms/rpb11/pmd1/rb11 pgec (4) /an7/rpc1/rc1 pged2/rpb10/cted11/pmd2/rb10 v dd v dd v ss v cap osc1/clki/rpa2/ra2 v ss osc2/clko/rpa3/pma0/ra3 rpc9/cted7/rc9 sosci/rpb4/rb4 tdo/rpb9/sda1/cted4/pmd3/rb9 sosco/rpa4/t1ck/cted9/pma1/ra4 rpc3/rc3 v ss v dd v dd pged3/rpb5/pmd7/rb5 pgec3/rpb6/pmd6/rb6 tdi/rpb7/cted3/pmd5/int0/rb7 tck/rpb8/scl1/cted10/pmd4/rb8 pic32mx130f064c pic32mx150f128c www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 8 preliminary ? 2011-2012 microchip technology inc. pin diagrams (continued) 36-pin vtla (1,2,3) = pins are up to 5v tolerant note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 11.3 ?peripheral pin select? for restrictions. 2: every i/o port pin (rax-rcx) can be used as a change notification pin (cnax-cncx). see section 11.0 ?i/o ports? for more information. 3: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. 4: this pin function is available on pic32mx2 30f064c and pic32mx250f128c devices only. pic32mx220f032c 1 pic32mx210f016c 10 33 32 31 30 29 28 2 3 4 5 6 24 23 22 21 20 19 11 12 13 14 15 7 8 9 34 35 36 16 17 18 27 26 25 pgec1/an3/c1inc/c2ina/rpb1/cted12/pmd1/rb1 pged1/an2/c1ind/c2inb/ c3ind/rpb0/pmd0/rb0 pgec3/v ref -/cv ref -/an1/rpa1/cted2/pmd6/ra1 pged3/v ref +/cv ref +/an0/c3inc/rpa0/cted1/pmd7/ra0 mclr av dd av ss an9/c3ina/rpb15/sck2/cted6/pmcs1/rb15 cv ref /an10/c3inb/rpb14/vbuson/sck1/cted5/rb14 an4/c1inb/c2ind/rpb2/sda2/cted13/pmd2/rb2 an11/rpb13/ctpls/pmrd/rb13 an5/c1ina/c2inc/rtcc /rpb3/scl2/pmwr/rb3 v usb 3 v 3 pged4 (4) /an6/rpc0/rc0 pgec2/rpb11/d-/rb11 pgec4 (4) /an7/rpc1/rc1 pged2/rpb10/d+/cted11/rb10 v dd v cap osc1/clki/rpa2/ra2 v ss osc2/clko/rpa3/pma0/ra3 rpc9/cted7/rc9 sosci/rpb4/rb4 tdo/rpb9/sda1/cted4/pmd3/rb9 sosco/rpa4/t1ck/cted9/pma1/ra4 an12/rpc3/rc3 v ss v dd v dd tms/rpb5/usbid/rb5 v bus tdi/rpb7/cted3/pmd5/int0/rb7 tck/rpb8/scl1/cted10/pmd4/rb8 v dd v ss pic32mx230f064c pic32mx250f128c www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 9 pic32mx1xx/2xx pin diagrams (continued) 44-pin qfn (1,2,3) = pins are up to 5v tolerant note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 11.3 ?peripheral pin select? for restrictions. 2: every i/o port pin (rax-rcx) can be used as a change notification pin (cnax-cncx). see section 11.0 ?i/o ports? for more information. 3: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. 4: this pin function is available on pic32mx1 30f064d and pic32mx150f128d devices only. rpb8/scl1/cted10/pmd4/rb8 rpb7/cted3/pmd5/int0/rb7 pgec3/rpb6/pmd6/rb6 pged3/rpb5/pmd7/rb5 v dd v ss rpc5/pma3/rc5 rpc4/pma4/rc4 rpc3/rc3 tdi/rpa9/pma9/ra9 sosco/rpa4/t1ck/cted9/ra4 44 43 42 41 40 39 38 37 36 35 34 rpb9/sda1/cted4/pmd3/rb9 1 33 sosci/rpb4/rb4 rpc6/pma1/rc6 2 32 tdo/rpa8/pma8/ra8 rpc7/pma0/rc7 3 31 osc2/clko/rpa3/ra3 rpc8/pma5/rc8 4 30 osc1/clki/rpa2/ra2 rpc9/cted7/pma6/rc9 5 29 v ss v ss 6 pic32mx110f016d 28 v dd v cap 7 27 an8/rpc2/pma2/rc2 pged2/rpb10/cted11/pmd2/rb10 8 26 an7/rpc1/rc1 pgec2/rpb11/pmd1/rb11 9 25 an6/rpc0/rc0 an12/pmd0/rb12 10 24 an5/c1ina /c2inc/rtcc/rpb3/scl2/rb3 an11/rpb13/ctpls/pmrd/rb13 11 23 an4/ c1inb/c2ind/rpb2/sda2/cted13/rb2 12 13 14 15 16 17 18 19 20 21 22 pged4 (4) /tms/pma10/ra10 pgec (4) /tck/cted8/pma7/ra7 cv ref /an10/c3inb/rpb14/sck1/cted5/pmwr/rb14 an9/c3ina/rpb15/sck2/cted6/pmcs1/rb15 av ss av dd mclr v ref +/cv ref +/an0/c3inc/rpa0/cted1/ra0 v ref -/cv ref -/an1/rpa1/cted2/ra1 pged1/an2/c1ind/c2inb/c3ind/rpb0/rb0 pgec1/an3/c1inc/c2ina/rpb1/cted12/rb1 pic32mx120f032d pic32mx130f064d pic32mx150f128d www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 10 preliminary ? 2011-2012 microchip technology inc. pin diagrams (continued) 44-pin qfn (1,2,3) = pins are up to 5v tolerant note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 11.3 ?peripheral pin select? for restrictions. 2: every i/o port pin (rax-rcx) can be used as a change notification pin (cnax-cncx). see section 11.0 ?i/o ports? for more information. 3: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. 4: this pin function is available on pic32mx2 30f064d and pic32mx250f128d devices only. rpb8/scl1/cted10/pmd4/rb8 rpb7/cted3/pmd5/int0/rb7 v bus rpb5/usbid/rb5 v dd v ss rpc5/pma3/rc5 rpc4/pma4/rc4 an12/rpc3/rc3 tdi/rpa9/pma9/ra9 sosco/rpa4/t1ck/cted9/ra4 44 43 42 41 40 39 38 37 36 35 34 1 33 sosci/rpb4/rb4 rpc6/pma1/rc6 2 32 tdo/rpa8/pma8/ra8 rpc7/pma0/rc7 3 31 osc2/clko/rpa3/ra3 rpc8/pma5/rc8 4 30 osc1/clki/rpa2/ra2 rpc9/cted7/pma6/rc9 5 29 v ss v ss 6 pic32mx210f016d 28 v dd v cap 7 27 an8/rpc2/pma2/rc2 8 26 an7/rpc1/rc1 pgec2/rpb11/d-/rb11 9 25 an6/rpc0/rc0 v usb 3 v 3 10 24 an5/c1ina/c2inc/rtcc/rpb3/scl2/pmwr/cnb3/rb3 an11/rpb13/ctpls/pmrd/rb13 11 23 an4/c1inb/c2ind/rpb2/sda2/cted13/pmd2/cnb2/rb2 12 13 14 15 16 17 18 19 20 21 22 pged (4) /tms/pma10/ra10 pgec (4) /tck/cted8/pma7/ra7 cv ref /an10/c3inb/rpb14/vb uson/sck1/cted5/rb14 an9/c3ina/rpb15/sck2/cted6/pmcs1/rb15 av ss av dd mclr pged3/v ref +/cv ref +/an0/c3inc/rpa0/cted1/pmd7/ra0 pgec3/v ref -/cv ref -/an1/rpa1/cted2/pmd6/ra1 pged1/an2/c1ind/c2inb/ c3ind/rpb0/pmd0/rb0 pgec1/an3/c1inc/c2ina/rpb1/cted12/pmd1/rb1 pged2/rpb10/d+/cted11/rb10 rpb9/sda1/cted4/pmd3/rb9 pic32mx220f032d pic32mx230f064d pic32mx250f128d www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 11 pic32mx1xx/2xx pin diagrams (continued) 44-pin tqfp (1,2,3) = pins are up to 5v tolerant note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 11.3 ?peripheral pin select? for restrictions. 2: every i/o port pin (rax-rcx) can be used as a change notification pin (cnax-cncx). see section 11.0 ?i/o ports? for more information. 3: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. 4: this pin function is available on pic32mx1 30f064d and pic32mx150f128d devices only. rpb8/scl1/cted10/pmd4/rb8 rpb7/cted3/pmd5/int0/rb7 pgec3/rpb6/pmd6/rb6 pged3/rpb5/pmd7/rb5 v dd v ss rpc5/pma3/rc5 rpc4/pma4/rc4 rpc3/rc3 tdi/rpa9/pma9/ra9 sosco/rpa4/t1ck/cted9/ra4 44 43 42 41 40 39 38 37 36 35 34 rpb9/sda1/cted4/pmd3/rb9 1 33 sosci/rpb4/rb4 rpc6/pma1/rc6 2 32 tdo/rpa8/pma8/ra8 rpc7/pma0/rc7 3 31 osc2/clko/rpa3/ra3 rpc8/pma5/rc8 4 30 osc1/clki/rpa2/ra2 rpc9/cted7/pma6/rc9 5 29 v ss v ss 6 pic32mx110f016d 28 v dd v cap 7 27 an8/rpc2/pma2/rc2 pged2/rpb10/cted11/pmd2/rb10 8 26 an7/rpc1/rc1 pgec2/rpb11/pmd1/rb11 9 25 an6/rpc0/rc0 an12/pmd0/rb12 10 24 an5/c1ina /c2inc/rtcc/rpb3/scl2/rb3 an11/rpb13/ctpls/pmrd/rb13 11 23 an4/ c1inb/c2ind/rpb2/sda2/cted13/rb2 12 13 14 15 16 17 18 19 20 21 22 pged (4) /tms/pma10/ra10 pgec (4) /tck/cted8/pma7/ra7 cv ref /an10/c3inb/rpb14/sck1/cted5/pmwr/rb14 an9/c3ina/rpb15/sck2/cted6/pmcs1/rb15 av ss av dd mclr v ref +/cv ref +/an0/c3inc/rpa0/cted1/ra0 v ref -/cv ref -/an1/rpa1/cted2/ra1 pged1/an2/c1ind/c2 inb/c3ind/rpb0/rb0 pgec1/an3/c1inc/c2ina/rpb1/cted12/rb1 pic32mx120f032d pic32mx130f064d pic32mx150f128d www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 12 preliminary ? 2011-2012 microchip technology inc. pin diagrams (continued) 44-pin vtla (1,2,3) = pins are up to 5v tolerant note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 11.3 ?peripheral pin select? for restrictions. 2: every i/o port pin (rax-rcx) can be used as a change notification pin (cnax-cncx). see section 11.0 ?i/o ports? for more information. 3: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. 4: this pin function is available on pic32mx1 30f064d and pic32mx150f128d devices only. rpb8/scl1/cted10/pmd4/rb8 rpb7/cted3/pmd5/int0/rb7 pgec3/rpb6/pmd6/rb6 pged3/rpb5/pmd7/rb5 v dd v ss rpc5/pma3/rc5 rpc4/pma4/rc4 rpc3/rc3 tdi/rpa9/pma9/ra9 sosco/rpa4/t1ck/cted9/ra4 rpb9/sda1/cted4/pmd3/rb9 sosci/rpb4/rb4 rpc6/pma1/rc6 tdo/rpa8/pma8/ra8 rpc7/pma0/rc7 osc2/clko/rpa3/ra3 rpc8/pma5/rc8 osc1/clki/rpa2/ra2 rpc9/cted7/pma6/rc9 v ss v ss pic32mx110f016d v dd v cap an8/rpc2/pma2/rc2 pged2/rpb10/cted11/pmd2/rb10 an7/rpc1/rc1 pgec2/rpb11/pmd1/rb11 an6/rpc0/rc0 an12/pmd0/rb12 an5/c1ina/c2inc/rtcc/rpb3/scl2/rb3 an4/c1inb/c2ind/rpb2/sda2/cted13/rb2 pgec (4) /tck/cted8/pma7/ra7 cv ref /an10/c3inb/rpb14/sck1/cted5/pmwr/rb14 an9/c3ina/rpb15/sck2/cted6/pmcs1/rb15 av ss av dd mclr v ref +/cv ref +/an0/c3inc/rpa0/cted1/ra0 v ref -/cv ref -/an1/rpa1/cted2/ra1 pged1/an2/c1ind/c2inb/c3ind/rpb0/rb0 pic32mx120f032d 1 10 33 32 31 30 29 28 2 3 4 5 6 24 23 22 21 20 19 11 12 13 14 15 7 8 9 34 35 36 16 17 18 27 26 25 37 38 39 40 41 42 43 44 pgec1/an3/c1inc/c2ina/rpb1/cted12/rb1 an11/rpb13/ctpls/pmrd/rb13 pic32mx130f064d pic32mx150f128d pged (4) /tms/pma10/ra10 www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 13 pic32mx1xx/2xx pin diagrams (continued) 44-pin tqfp (1,2,3) = pins are up to 5v tolerant note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 11.3 ?peripheral pin select? for restrictions. 2: every i/o port pin (rax-rcx) can be used as a change notification pin (cnax-cncx). see section 11.0 ?i/o ports? for more information. 3: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. 4: this pin function is available on pic32mx2 30f064d and pic32mx250f128d devices only. rpb8/scl1/cted10/pmd4/rb8 rpb7/cted3/pmd5/int0/rb7 v bus rpb5/usbid/rb5 v dd v ss rpc5/pma3/rc5 rpc4/pma4/rc4 an12/rpc3/rc3 tdi/rpa9/pma9/ra9 sosco/rpa4/t1ck/cted9/ra4 44 43 42 41 40 39 38 37 36 35 34 1 33 sosci/rpb4/rb4 rpc6/pma1/rc6 2 32 tdo/rpa8/pma8/ra8 rpc7/pma0/rc7 3 31 osc2/clko/rpa3/ra3 rpc8/pma5/rc8 4 30 osc1/clki/rpa2/ra2 rpc9/cted7/pma6/rc9 5 29 v ss v ss 6 pic32mx210f016d 28 v dd v cap 7 27 an8/rpc2/pma2/rc2 8 26 an7/rpc1/rc1 pgec2/rpb11/d-/rb11 9 25 an6/rpc0/rc0 v usb 3 v 3 10 24 an5/c1ina/c2inc/rtcc/rpb3/scl2/pmwr/cnb3/rb3 an11/rpb13/ctpls/pmrd/rb13 11 23 an4/c1inb/c2ind/rpb2/sda2/cted13/pmd2/cnb2/rb2 12 13 14 15 16 17 18 19 20 21 22 pged (4) /tms/pma10/ra10 pgec (4) /tck/cted8/pma7/ra7 cv ref /an10/c3inb/rpb14/vbuson/sck1/cted5/rb14 an9/c3ina/rpb15/sck2/cted6/pmcs1/rb15 av ss av dd mclr pged3/v ref +/cv ref +/an0/c3inc/rpa0 /cted1/pmd7/ra0 pgec3/v ref -/cv ref -/an1/rpa1/cted2/pmd6/ra1 pged1/an2/c1ind/c2inb/ c3ind/rpb0/pmd0/rb0 pgec1/an3/c1inc/c2ina/rpb1/cted12/pmd1/rb1 pged2/rpb10/d+/cted11/rb10 rpb9/sda1/cted4/pmd3/rb9 pic32mx220f032d pic32mx230f064d pic32mx250f128d www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 14 preliminary ? 2011-2012 microchip technology inc. pin diagrams (continued) 44-pin vtla (1,2,3) = pins are up to 5v tolerant note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 11.3 ?peripheral pin select? for restrictions. 2: every i/o port pin (rax-rcx) can be used as a change notification pin (cnax-cncx). see section 11.0 ?i/o ports? for more information. 3: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. 4: this pin function is available on pic32mx2 30f064d and pic32mx250f128d devices only. rpb8/scl1/cted10/pmd4/rb8 rpb7/cted3/pmd5/int0/rb7 v bus rpb5/usbid/rb5 v dd v ss rpc5/pma3/rc5 rpc4/pma4/rc4 an12/rpc3/rc3 tdi/rpa9/pma9/ra9 sosco/rpa4/t1ck/cted9/ra4 sosci/rpb4/rb4 rpc6/pma1/rc6 tdo/rpa8/pma8/ra8 rpc7/pma0/rc7 osc2/clko/rpa3/ra3 rpc8/pma5/rc8 osc1/clki/rpa2/ra2 rpc9/cted7/pma6/rc9 v ss v ss v dd v cap an8/rpc2/pma2/rc2 an7/rpc1/rc1 pgec2/rpb11/d-/rb11 an6/rpc0/rc0 v usb 3 v 3 an5/c1ina/c2inc/rtcc/rpb3/scl2/pmwr/cnb3/rb3 an11/rpb13/ctpls/pmrd/rb13 an4/c1inb/c2ind/rpb2/sda2/cted13/pmd2/cnb2/rb2 pged (4) /tms/pma10/ra10 pgec (4) /tck/cted8/pma7/ra7 cv ref /an10/c3inb/rpb14/vb uson/sck1/cted5/rb14 an9/c3ina/rpb15/sck2/cted6/pmcs1/rb15 av ss av dd mclr pged3/v ref +/cv ref +/an0/c3inc/rpa0/cted1/pmd7/ra0 pgec3/v ref -/cv ref -/an1/rpa1/cted2/pmd6/ra1 pged1/an2/c1ind/c2inb/c3ind/rpb0/pmd0/rb0 pgec1/an3/c1inc/c2ina/rpb1/cted12/pmd1/rb1 pged2/rpb10/d+ /cted11/rb10 rpb9/sda1/cted4/pmd3/rb9 pic32mx210f016d pic32mx220f032d 1 10 33 32 31 30 29 28 2 3 4 5 6 24 23 22 21 20 19 11 12 13 14 15 7 8 9 34 35 36 16 17 18 27 26 25 37 38 39 40 41 42 43 44 pic32mx230f064d pic32mx250f128d www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 15 pic32mx1xx/2xx table of contents 1.0 device overview ............................................................................................................. ........................................................... 19 2.0 guidelines for getting started wi th 32-bit microcontrollers ................................................................. ....................................... 27 3.0 cpu......................................................................................................................... ................................................................... 33 4.0 memory organization ......................................................................................................... ........................................................ 37 5.0 flash program memory........................................................................................................ ...................................................... 79 6.0 resets ...................................................................................................................... .................................................................. 83 7.0 interrupt controller ........................................................................................................ ............................................................. 87 8.0 oscillator configuration .................................................................................................... .......................................................... 95 9.0 direct memory access (dma) controller ....................................................................................... .......................................... 105 10.0 usb on-the-go (otg)........................................................................................................ .................................................... 121 11.0 i/o ports .................................................................................................................. ................................................................. 143 12.0 timer1 ..................................................................................................................... ................................................................. 151 13.0 timer2/3, timer4/5 ......................................................................................................... .......................................................... 155 14.0 input capture.............................................................................................................. .............................................................. 159 15.0 output compare............................................................................................................. .......................................................... 163 16.0 serial peripheral interface (spi).......................................................................................... ..................................................... 165 17.0 inter-integrated circuit? (i 2 c?)............................................................................................................................ .................. 173 18.0 universal asynchronous receiv er transmitter (uart) ......................................................................... .................................. 179 19.0 parallel master port (pmp)................................................................................................. ...................................................... 185 20.0 real-time clock and calendar (rtcc)........................................................................................ ........................................... 193 21.0 10-bit analog-to-digital converter (adc) ................................................................................... .............................................. 203 22.0 comparator ................................................................................................................. ............................................................. 211 23.0 comparator voltage reference (cv ref ) .............................................................................................................................. ... 215 24.0 charge time measurement unit (ctmu) ....................................................................................... ........................................ 217 25.0 power-saving features ..................................................................................................... ...................................................... 221 26.0 special features ........................................................................................................... ........................................................... 225 27.0 instruction set ............................................................................................................ .............................................................. 239 28.0 development support........................................................................................................ ....................................................... 241 29.0 electrical characteristics ................................................................................................. ......................................................... 245 30.0 dc and ac device characteristics graphs.................................................................................... .......................................... 285 31.0 packaging information...................................................................................................... ........................................................ 289 the microchip web site ......................................................................................................... ............................................................ 315 customer change notification service ........................................................................................... ................................................... 315 customer support ............................................................................................................... ............................................................... 315 reader response ................................................................................................................ .............................................................. 316 product identification system .................................................................................................. .......................................................... 317 www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 16 preliminary ? 2011-2012 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publicat ions to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments r egarding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for curren t devices. as device/documen tation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a partic ular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 17 pic32mx1xx/2xx referenced sources this device data sheet is based on the following individual chapters of the ?pic32 family reference manual? . these documents should be considered as the general reference for t he operation of a particular module or device feature. ? section 1. ?introduction? (ds61127) ? section 2. ?cpu? (ds61113) ? section 3. ?memory organization? (ds61115) ? section 5. ?flash program memory? (ds61121) ? section 6. ?oscillator configuration? (ds61112) ? section 7. ?resets? (ds61118) ? section 8. ?interrupt controller? (ds61108) ? section 9. ?watchdog timer and power-up timer? (ds61114) ? section 10. ?power-saving features? (ds61130) ? section 12. ?i/o ports? (ds61120) ? section 13. ?parallel master port (pmp)? (ds61128) ? section 14. ?timers? (ds61105) ? section 15. ?input capture? (ds61122) ? section 16. ?output compare? (ds61111) ? section 17. ?10-bit analog-to -digital converter (adc)? (ds61104) ? section 19. ?comparator? (ds61110) ? section 20. ?comparator voltage reference (cv ref )? (ds61109) ? section 21. ?universal asynchronous receiver transmitter (uart)? (ds61107) ? section 23. ?serial peri pheral interface (spi)? (ds61106) ? section 24. ?inter-integrated circuit? (i 2 c?)? (ds61116) ? section 27. ?usb on-the-go (otg)? (ds61126) ? section 29. ?real-time clock and calendar (rtcc)? (ds61125) ? section 31. ?direct memory access (dma) controller? (ds61117) ? section 32. ?configuration? (ds61124) ? section 33. ?programming and diagnostics? (ds61129) ? section 37. ?charge time measurement unit (ctmu)? (ds61167) note: to access the documents listed below, browse to the documentation section of the microchip web site ( www.microchip.com ). www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 18 preliminary ? 2011-2012 microchip technology inc. notes: www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 19 pic32mx1xx/2xx 1.0 device overview this document contains devic e-specific information for pic32mx1xx/2xx devices. figure 1-1 illustrates a general block diagram of the core and peripheral modules in the pic32mx1xx/2xx family of devices. table 1-1 lists the functions of the various pins shown in the pinout diagrams. figure 1-1: block diagram (1) note 1: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the related section of the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note 1: some features are not available on all device va riants. refer to the family features tables ( tab l e 1 and table 2 ) for availability. uart1-2 comparators 1-3 porta remappable portb ctmu jtag priority dmac icd mips32 ? m4k ? is ds ejtag int bus matrix data ram peripheral bridge 128 128-bit wide flash 32 32 32 32 peripheral bus clocked by pbclk program flash memory controller 32 32 32 interrupt controller bscan portc pmp i2c1-2 spi1-2 ic1-5 pwm oc1-5 osc1/clki osc2/clko v dd , v ss timing generation mclr power-up timer oscillator start-up timer power-on reset watchdog timer brown-out reset precision reference band gap frc/lprc oscillators regulator voltage v cap osc/s osc oscillators pll dividers sysclk pbclk peripheral bus clocked by sysclk usb pll-usb usbclk 32 rtcc 10-bit adc timer1-5 32 32 cpu core pins www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 20 preliminary ? 2011-2012 microchip technology inc. table 1-1: pinout i/o descriptions pin name pin number (1) pin type buffer type description 28-pin qfn 28-pin ssop/ spdip/ soic 36-pin vtla 44-pin qfn/ tqfp/ vtla an0 27 2 33 19 i analog analog input channels. an1 28 3 34 20 i analog an2 1 4 35 21 i analog an3 2 5 36 22 i analog an4 3 6 1 23 i analog an5 4 7 2 24 i analog an6 ? ? 3 25 i analog an7 ? ? 4 26 i analog an8 ? ? ? 27 i analog an9 23262915ianalog an10 22 25 28 14 i analog an11 21 24 27 11 i analog an12 20 (2) 23 (2) 26 (2) 10 (2) ianalog 11 (3) 36 (3) clki 6 9 7 30 i st/cmos external clock source input. always associated with osc1 pin function. clko 7 10 8 31 o ? oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. optionally functions as clko in rc and ec modes. always associated with osc2 pin function. osc1 6 9 7 30 i st/cmos oscillator crystal input. st buffer when configured in rc mode; cmos otherwise. osc2 7 10 8 31 i/o ? oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. optionally functions as clko in rc and ec modes. sosci 8 11 9 33 i st/cmos 32.768 khz low-power oscillator crystal input; cmos otherwise. sosco 9 12 10 34 o ? 32.768 khz low-power oscillator crystal output. refclki pps pps pps pps i st reference input clock refclko pps pps pps pps o ? reference output clock ic1 pps pps pps pps i st capture inputs 1-5 ic2 pps pps pps pps i st ic3 pps pps pps pps i st ic4 pps pps pps pps i st ic5 pps pps pps pps i st legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer pps = pe ripheral pin select ? = n/a note 1: pin numbers are provided for reference only. see the ? pin diagrams ? section for device pin availability. 2: pin number for pic32mx1xx devices only. 3: pin number for pic32mx2xx devices only. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 21 pic32mx1xx/2xx oc1 pps pps pps pps o ? output compare output 1 oc2 pps pps pps pps o ? output compare output 2 oc3 pps pps pps pps o ? output compare output 3 oc4 pps pps pps pps o ? output compare output 4 oc5 pps pps pps pps o ? output compare output 5 ocfa pps pps pps pps i st output compare fault a input ocfb pps pps pps pps i st output compare fault b input int0 13 16 17 43 i st external interrupt 0 int1 pps pps pps pps i st external interrupt 1 int2 pps pps pps pps i st external interrupt 2 int3 pps pps pps pps i st external interrupt 3 int4 pps pps pps pps i st external interrupt 4 ra0 27 2 33 19 i/o st porta is a bidirectional i/o port ra1 28 3 34 20 i/o st ra2 6 9 7 30 i/o st ra3 7 10 8 31 i/o st ra4 9 12 10 34 i/o st ra7 ? ? ? 13 i/o st ra8 ? ? ? 32 i/o st ra9 ? ? ? 35 i/o st ra10 ? ? ? 12 i/o st rb0 1 4 35 21 i/o st portb is a bidirectional i/o port rb1 2 5 36 22 i/o st rb2 3 6 1 23 i/o st rb3 4 7 2 24 i/o st rb4 8 11 9 33 i/o st rb5 11 141541i/ost rb6 12 (2) 15 (2) 16 (2) 42 (2) i/o st rb7 13161743i/ost rb8 14171844i/ost rb9 15 18 19 1 i/o st rb10 18 21 24 8 i/o st rb11 19 22 25 9 i/o st rb12 20 (2) 23 (2) 26 (2) 10 (2) i/o st rb13 21 24 27 11 i/o st rb14 22 25 28 14 i/o st rb15 23 26 29 15 i/o st table 1-1: pinout i/o descriptions (continued) pin name pin number (1) pin type buffer type description 28-pin qfn 28-pin ssop/ spdip/ soic 36-pin vtla 44-pin qfn/ tqfp/ vtla legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer pps = peripheral pin select ? = n/a note 1: pin numbers are provided for reference only. see the ? pin diagrams ? section for device pin availability. 2: pin number for pic32mx1xx devices only. 3: pin number for pic32mx2xx devices only. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 22 preliminary ? 2011-2012 microchip technology inc. rc0 ? ? 3 25 i/o st portc is a bidirectional i/o port rc1 ? ? 4 26 i/o st rc2 ? ? ? 27 i/o st rc3 ? ? 11 36 i/o st rc4 ? ? ? 37 i/o st rc5 ? ? ? 38 i/o st rc6 ? ? ? 2 i/o st rc7 ? ? ? 3 i/o st rc8 ? ? ? 4 i/o st rc9 ? ? 20 5 i/o st t1ck 9 12 10 34 i st timer1 external clock input t2ck pps pps pps pps i st timer2 external clock input t3ck pps pps pps pps i st timer3 external clock input t4ck pps pps pps pps i st timer4 external clock input t5ck pps pps pps pps i st timer5 external clock input u1cts pps pps pps pps i st uart1 clear to send u1rts pps pps pps pps o ? uart1 ready to send u1rx pps pps pps pps i st uart1 receive u1tx pps pps pps pps o ? uart1 transmit u2cts pps pps pps pps i st uart2 clear to send u2rts pps pps pps pps o ? uart2 ready to send u2rx pps pps pps pps ist uart2 receive u2tx pps pps pps pps o? uart2 transmit sck1 22 25 28 14 i/o st synchronous serial clock input/output for spi1 sdi1 pps pps pps pps ist spi1 data in sdo1 pps pps pps pps o? spi1 data out ss1 pps pps pps pps i/o st spi1 slave synchronization or frame pulse i/o sck2 23 26 29 15 i/o st synchronous serial clock input/output for spi2 sdi2 pps pps pps pps ist spi2 data in sdo2 pps pps pps pps o? spi2 data out ss2 pps pps pps pps i/o st spi2 slave synchronization or frame pulse i/o scl1 14 17 18 44 i/o st synchronous serial clock input/output for i2c1 table 1-1: pinout i/o descriptions (continued) pin name pin number (1) pin type buffer type description 28-pin qfn 28-pin ssop/ spdip/ soic 36-pin vtla 44-pin qfn/ tqfp/ vtla legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer pps = pe ripheral pin select ? = n/a note 1: pin numbers are provided for reference only. see the ? pin diagrams ? section for device pin availability. 2: pin number for pic32mx1xx devices only. 3: pin number for pic32mx2xx devices only. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 23 pic32mx1xx/2xx sda1 15 18 19 1 i/o st synchronous serial data input/output for i2c1 scl2 4 7 2 24 i/o st synchronous serial clock input/output for i2c2 sda2 3 6 1 23 i/o st synchronous serial data input/output for i2c2 tms 19 (2) 22 (2) 25 (2) 12 i st jtag test mode select pin 11 (3) 14 (3) 15 (3) tck 14 17 18 13 i st jtag test clock input pin tdi 13 16 17 35 o ? jtag test data input pin tdo 15 18 19 32 o ? jtag test data output pin rtcc 4 7 2 24 i st real-time clock alarm output c vref - 28 3 34 20 i analog comparator voltage reference (low) c vref + 27 2 33 19 i analog comparator voltage reference (high) c vrefout 22 25 28 14 o analog comparator voltage reference output c1ina 4 7 2 24 i analog comparator inputs c1inb 3 6 1 23 i analog c1inc 2 5 36 22 i analog c1ind 1 4 35 21 i analog c2ina 2 5 36 22 i analog c2inb 1 4 35 21 i analog c2inc 4 7 2 24 i analog c2ind 3 6 1 23 i analog c3ina 23262915ianalog c3inb 22252814ianalog c3inc 27 2 33 19 i analog c3ind 1 4 35 21 i analog c1out pps pps pps pps o ? comparator outputs c2out pps pps pps pps o ? c3out pps pps pps pps o ? table 1-1: pinout i/o descriptions (continued) pin name pin number (1) pin type buffer type description 28-pin qfn 28-pin ssop/ spdip/ soic 36-pin vtla 44-pin qfn/ tqfp/ vtla legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer pps = peripheral pin select ? = n/a note 1: pin numbers are provided for reference only. see the ? pin diagrams ? section for device pin availability. 2: pin number for pic32mx1xx devices only. 3: pin number for pic32mx2xx devices only. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 24 preliminary ? 2011-2012 microchip technology inc. pma0 7 10 8 3 i/o ttl/st parallel master port address bit 0 input (buffered slave modes) and output (master modes) pma1 9 12 10 2 i/o ttl/st parallel master port address bit 1 input (buffered slave modes) and output (master modes) pma2 ? ? 27 o ? parallel master port address (demultiplexed master modes) pma3 ? ? 38 o ? pma4 ? ? 37 o ? pma5 ? ? 4 o ? pma6 ? ? 5 o ? pma7 ? ? 13 o ? pma8 ? ? 32 o ? pma9 ? ? 35 o ? pma10 ? ? 12 o ? pmcs1 23 26 29 15 o ? parallel master port chip select 1 strobe pmd0 20 (2) 23 (2) 26 (2) 10 (2) i/o ttl/st parallel master port data (demultiplexed master mode) or address/data (multiplexed master modes) 1 (3) 4 (3) 35 (3) 21 (3) pmd1 19 (2) 22 (2) 25 (2) 9 (2) i/o ttl/st 2 (3) 5 (3) 36 (3) 22 (3) pmd2 18 (2) 21 (2) 24 (2) 8 (2) i/o ttl/st 3 (3) 6 (3) 1 (3) 23 (3) pmd3 15 18 19 1 i/o ttl/st pmd4 14 17 18 44 i/o ttl/st pmd5 13 16 17 43 i/o ttl/st pmd6 12 (2) 15 (2) 16 (2) 42 (2) i/o ttl/st 28 (3) 3 (3) 34 (3) 20 (3) pmd7 11 (2) 14 (2) 15 (2) 41 (2) i/o ttl/st 27 (3) 2 (3) 33 (3) 19 (3) pmrd 21 24 27 11 o ? parallel master port read strobe pmwr 22 (2) 25 (2) 28 (2) 14 (2) o ? parallel master port write strobe 4 (3) 7 (3) 2 (3) 24 (3) v bus 12 15 16 42 i analog usb bus power monitor v usb 3 v 3 20 23 26 10 p ? usb internal transceiver supply. if the usb module is not used, this pin must be connected to v dd . v buson 22 25 28 14 o ? usb host and otg bus power control output d+ 18 21 24 8 i/o analog usb d+ d- 19 22 25 9 i/o analog usb d- table 1-1: pinout i/o descriptions (continued) pin name pin number (1) pin type buffer type description 28-pin qfn 28-pin ssop/ spdip/ soic 36-pin vtla 44-pin qfn/ tqfp/ vtla legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer pps = pe ripheral pin select ? = n/a note 1: pin numbers are provided for reference only. see the ? pin diagrams ? section for device pin availability. 2: pin number for pic32mx1xx devices only. 3: pin number for pic32mx2xx devices only. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 25 pic32mx1xx/2xx usbid 11 14 15 41 i st usb otg id detect cted1 27 2 33 19 i st ctmu external edge input cted2 28 3 34 20 i st cted313161743ist cted4 15 18 19 1 i st cted522252814ist cted623262915ist cted7 ? ? 20 5 i st cted8 ? ? ? 13 i st cted9 9 12 10 34 i st cted10 14 17 18 44 i st cted11 18 21 24 8 i st cted12 2 5 36 22 i st cted13 3 6 1 23 i st ctpls 21 24 27 11 o ? ctmu pulse output pged1 1 4 35 21 i/o st data i/o pi n for programming/debugging communication channel 1 pgec1 2 5 36 22 i st clock input pin for programming/debugging communication channel 1 pged2 18 21 24 8 i/o st data i/o pi n for programming/debugging communication channel 2 pgec2 19 22 25 9 i st clock input pin for programming/debugging communication channel 2 pged3 11 (2) 14 (2) 15 (2) 41 (2) i/o st data i/o pin for programming/debugging communication channel 3 27 (3) 2 (3) 33 (3) 19 (3) pgec3 12 (2) 15 (2) 16 (2) 42 (2) ist clock input pin for programming/ debugging communication channel 3 28 (3) 3 (3) 34 (3) 20 (3) pged4 ? ? 3 12 i/o st data i/o pin for programming/debugging communication channel 4 pgec4 ? ? 4 13 ist clock input pin for programming/ debugging communication channel 4 table 1-1: pinout i/o descriptions (continued) pin name pin number (1) pin type buffer type description 28-pin qfn 28-pin ssop/ spdip/ soic 36-pin vtla 44-pin qfn/ tqfp/ vtla legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer pps = peripheral pin select ? = n/a note 1: pin numbers are provided for reference only. see the ? pin diagrams ? section for device pin availability. 2: pin number for pic32mx1xx devices only. 3: pin number for pic32mx2xx devices only. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 26 preliminary ? 2011-2012 microchip technology inc. mclr 26 1 32 18 i/p st master clear (reset) input. this pin is an active-low reset to the device. av dd 25 28 31 17 p ? positive supply for analog modules. this pin must be connected at all times. av ss 24 27 30 16 p ? ground reference for analog modules v dd 10 13 5, 13, 14, 23 28, 40 p ? positive supply for peripheral logic and i/o pins v cap 17 20 22 7 p ? cpu logic filter capacitor connection v ss 5, 16 8, 19 6, 12, 21 6, 29, 39 p ? ground reference for logic and i/o pins. this pin must be connected at all times. v ref + 27 2 33 19 i analog analog voltage reference (high) input v ref - 28 3 34 20 i analog analog voltage reference (low) input table 1-1: pinout i/o descriptions (continued) pin name pin number (1) pin type buffer type description 28-pin qfn 28-pin ssop/ spdip/ soic 36-pin vtla 44-pin qfn/ tqfp/ vtla legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer pps = pe ripheral pin select ? = n/a note 1: pin numbers are provided for reference only. see the ? pin diagrams ? section for device pin availability. 2: pin number for pic32mx1xx devices only. 3: pin number for pic32mx2xx devices only. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 27 pic32mx1xx/2xx 2.0 guidelines for getting started with 32-bit microcontrollers 2.1 basic connection requirements getting started with the pic32mx1xx/2xx family of 32-bit microcontrollers (mcus) requires attention to a minimal set of device pin connections before proceed- ing with development. the following is a list of pin names, which must always be connected: ? all v dd and v ss pins (see section 2.2 ?decoupling capacitors? ) ? all av dd and av ss pins, even if the adc module is not used (see section 2.2 ?decoupling capacitors? ) ?v cap pin (see section 2.3 ?capacitor on internal voltage regulator (v cap )? ) ?mclr pin (see section 2.4 ?master clear (mclr) pin? ) ? pgecx/pgedx pins, used for in-circuit serial programming (icsp?) and debugging purposes (see section 2.5 ?icsp pins? ) ? osc1 and osc2 pins, when external oscillator source is used (see section 2.7 ?externa l oscillator pins? ) the following pin may be required, as well: v ref +/v ref - pins, used when external voltage reference for the adc module is implemented. 2.2 decoupling capacitors the use of decoupling capacitors on power supply pins, such as v dd , v ss , av dd and av ss is required. see figure 2-1 . consider the following criteria when using decoupling capacitors: ? value and type of capacitor: a value of 0.1 f (100 nf), 10-20v is recommended. the capacitor should be a low equivalent series resistance (low- esr) capacitor and have resonance frequency in the range of 20 mhz and higher. it is further recommended that ceramic capacitors be used. ? placement on the printed circuit board: the decoupling capacitors should be placed as close to the pins as possible. it is recommended that the capacitors be placed on the same side of the board as the device. if space is constricted, the capacitor can be placed on another layer on the pcb using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. ? handling high frequency noise: if the board is experiencing high frequency noise, upward of tens of mhz, add a second ceramic-type capacitor in par- allel to the above described decoupling capacitor. the value of the second capacitor can be in the range of 0.01 f to 0.001 f. place this second capacitor next to the prim ary decoupling capacitor. in high-speed circuit designs, consider implement- ing a decade pair of capacitances as close to the power and ground pins as possible. for example, 0.1 f in parallel with 0.001 f. ? maximizing performance: on the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. this ensures that the decou- pling capacitors are first in the power chain. equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing pcb track inductance. figure 2-1: recommended minimum connection note 1: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the related section of the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: the av dd and av ss pins must be connected, regardless of adc use and the adc voltage reference source. pic32 v dd v ss v dd v ss v ss v dd av dd av ss v dd v ss c r v dd mclr 0.1 f ceramic v cap 10 r1 c bp 0.1 f ceramic c bp 0.1 f ceramic c bp 0.1 f ceramic c bp 0.1 f ceramic c bp c efc v usb 3 v 3 (1) note 1: if the usb module is not used, this pin must be connected to v dd . www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 28 preliminary ? 2011-2012 microchip technology inc. 2.2.1 bulk capacitors the use of a bulk capacitor is recommended to improve power supply stability. typical values range from 4.7 f to 47 f. this capacitor sh ould be located as close to the device as possible. 2.3 capacitor on internal voltage regulator (v cap ) 2.3.1 internal regulator mode a low-esr (1 ohm) capaci tor is required on the v cap pin, which is used to stabilize the internal voltage regu- lator output. the v cap pin must not be connected to v dd , and must have a c efc capacitor, with at least a 6v rating, connected to ground. the type can be ceramic or tantalum. refer to section 29.0 ?electrical characteristics? for additional information on c efc specifications. 2.4 master clear (mclr ) pin the mclr pin provides for two specific device functions: ? device reset ? device programming and debugging pulling the mclr pin low generates a device reset. figure 2-2 illustrates a typical mclr circuit. during device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. device programmers and debuggers drive the mclr pin. consequently, specific voltage levels (v ih and v il ) and fast signal transitions must not be adversely affected. therefore, specific values of r and c will need to be adjusted based on the application and pcb requirements. for example, as illustrated in figure 2-2 , it is recommended that the capaci tor c, be isolated from the mclr pin during programming and debugging operations. place the components illustrated in figure 2-2 within one-quarter inch (6 mm) from the mclr pin. figure 2-2: example of mclr pin connections note 1: r 10 k is recommended. a suggested start- ing value is 10 k . ensure that the mclr pin v ih and v il specifications are met. 2: r1 470 will limit any current flowing into mclr from the external capacitor c, in the event of mclr pin breakdown, due to electrostatic discharge (esd) or electrical overstress (eos). ensure that the mclr pin v ih and v il specifications are met. 3: the capacitor can be sized to prevent uninten- tional resets from brief glitches or to extend the device reset period during por. c (3) r1 (2) r (1) v dd mclr pic32 jp www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 29 pic32mx1xx/2xx 2.5 icsp pins the pgecx and pgedx pins are used for in-circuit serial programming? (icsp?) and debugging pur- poses. it is recommended to keep the trace length between the icsp connector and the icsp pins on the device as short as possible. if the icsp connector is expected to experience an esd event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100 ohms. pull-up resistors, series diodes and capacitors on the pgecx and pgedx pins are not recommended as they will interfere with the programmer/debugger communi- cations to the device. if such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. alternatively, refer to t he ac/dc characteristics and timing requirements information in the respective device flash programming spec ification for information on capacitive loading limits and pin input voltage high (v ih ) and input low (v il ) requirements. ensure that the ?communication channel select? (i.e., pgecx/pgedx pins) programmed into the device matches the physical con nections for the icsp to mplab ? icd 3 or mplab real ice?. for more information on icd 3 and real ice connection requirements, refer to the following documents that are available on the microchip web site. ? ?using mplab ? icd 3? (poster) ds51765 ? ?mplab ? icd 3 design advisory? ds51764 ? ?mplab ? real ice? in-circuit debugger user?s guide? ds51616 ? ?using mplab ? real ice? emulator? (poster) ds51749 2.6 jtag the tms, tdo, tdi and tck pins are used for testing and debugging according to the joint test action group (jtag) standard. it is recommended to keep the trace length between the jtag connector and the jtag pins on the device as short as possible. if the jtag connector is expected to experience an esd event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100 ohms. pull-up resistors, series diodes and capacitors on the tms, tdo, tdi and tck pins are not recommended as they will interfere with the programmer/debugger communications to the device. if such discrete compo- nents are an application requirement, they should be removed from the circuit during programming and debugging. alternatively, refer to the ac/dc character- istics and timing requirements information in the respective device flash programming specification for information on capacitive loading limits and pin input voltage high (v ih ) and input low (v il ) requirements. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 30 preliminary ? 2011-2012 microchip technology inc. 2.7 external oscillator pins many mcus have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to section 8.0 ?oscillator configuration? for details). the oscillator circuit should be placed on the same side of the board as the device. also, place the oscillator cir- cuit close to the respective oscillator pins, not exceed- ing one-half inch (12 mm) distance between them. the load capacitors should be placed next to the oscillator itself, on the same side of the board. use a grounded copper pour around the oscilla tor circuit to isolate them from surrounding circuits. the grounded copper pour should be routed directly to the mcu ground. do not run any signal traces or po wer traces inside the ground pour. also, if using a two-sided board, avoid any traces on the other side of the boa rd where the crystal is placed. a suggested layout is illustrated in figure 2-3 . figure 2-3: suggested oscillator circuit placement 2.8 configuration of analog and digital pins during icsp operations if mplab icd 2, icd 3 or real ice is selected as a debugger, it automatically init ializes all of the analog-to- digital input pins (anx) as ?digital? pins by setting all bits in the adpcfg register. the bits in this register that correspond to the analog- to-digital pins that are initialized by mplab icd 2, icd 3 or real ice, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. if your application needs to use certain analog-to-digital pins as analog input pins during the debug session, the user application must clear the corresponding bits in the adpcfg register during initialization of the adc module. when mplab icd 2, icd 3 or real ice is used as a programmer, the user application firmware must cor- rectly configure the adpcfg register. automatic initial- ization of this register is only done during debugger operation. failure to correct ly configure the register(s) will result in all analog-to-digital pins being recognized as analog input pins, resulting in the port value being read as a logic ? 0 ?, which may affect user application functionality. 2.9 unused i/os unused i/o pins should not be allowed to float as inputs. they can be config ured as outputs and driven to a logic-low state. alternatively, inputs can be reserved by connecting the pin to v ss through a 1k to 10k resistor and configuring the pin as an input. main oscillator guard ring guard trace secondary oscillator www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 31 pic32mx1xx/2xx 2.10 typical application connection examples examples of typical application connections are shown in figure 2-4 and figure 2-5 . figure 2-4: capacitive touch sensing with graphics application figure 2-5: audio playback application ctmu current source adc microchip mtouch? library user application microchip graphics library read the touch sensors process samples display data parallel master port lcd controller frame buffer display controller pmpd<7:0> lcd panel pic32mx120f032d to an6 to an7 to an8 to an11 c1 r3 c2 r2 r3 r1 c5 c5 c5 c1 r1 r1 r1 c3 r2 c3 r2 c1 r2 c2 r3 c2 r3 c3 an0 an1 an11 to a n 0 to a n 1 to an 5 an9 pmpwr to a n 9 r1 c4 r2 c4 r3 c4 audio codec display pmp i 2 s spi usb usb pmpd<7:0> 3 3 stereo headphones speaker pic32mx220f032d host pmpwr mmc sd 3 sdi www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 32 preliminary ? 2011-2012 microchip technology inc. notes: www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 33 pic32mx1xx/2xx 3.0 cpu the the mips32 ? m4k ? processor core is the heart of the pic32mx1xx/2xx family processor. the cpu fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of instruction execution to the proper destinations. 3.1 features ? 5-stage pipeline ? 32-bit address and data paths ? mips32 ? enhanced architecture (release 2) - multiply-accumulate and multiply-subtract instructions - targeted multiply instruction - zero/one detect instructions - wait instruction - conditional move instructions ( movn , movz ) - vectored interrupts - programmable exception vector base - atomic interrupt enable/disable - gpr shadow registers to minimize latency for interrupt handlers - bit field manipulation instructions ? mips16e ? code compression - 16-bit encoding of 32-bit instructions to improve code density - special pc-relative instructions for efficient loading of addresses and constants - save and restore macro instructions for setting up and tearing down stack frames within subroutines - improved support for handling 8 and 16-bit data types ? simple fixed mapping translation (fmt) mechanism ? simple dual bus interface - independent 32-bit address and data busses - transactions can be aborted to improve interrupt latency ? autonomous multiply/divide unit - maximum issue rate of one 32x16 multiply per clock - maximum issue rate of one 32x32 multiply every other clock - early-in iterative divide. minimum 11 and maximum 33 clock latency (dividend ( rs ) sign extension-dependent) ? power control - minimum frequency: 0 mhz - low-power mode (triggered by wait instruction) - extensive use of local gated clocks ? ejtag debug and instruction trace - support for single stepping - virtual instruction and data address/value - breakpoints figure 3-1: mips32 ? m4k ? processor core block diagram note 1: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 2. ?cpu? (ds61113) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). resources for the mips32 ? m4k ? processor core are available at http://www.mips.com . 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. dual bus i/f system coprocessor mdu fmt tap ejtag power management off-chip debug i/f execution core (rf/alu/shift) bus matrix bus interface cpu www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 34 preliminary ? 2011-2012 microchip technology inc. 3.2 architecture overview the mips32 ? m4k ? processor core contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. the following blocks are in cluded with the core: ? execution unit ? multiply/divide unit (mdu) ? system control coprocessor (cp0) ? fixed mapping translation (fmt) ? dual internal bus interfaces ? power management ? mips16e support ? enhanced jtag (ejtag) controller 3.2.1 execution unit the mips32 ? m4k ? processor core execution unit implements a load/store architecture with single-cycle alu operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. the core contains thirty-two 32-bit general purpose registers (gprs) used for integer operations and address calculation. one additional register file shadow set (containing thirty-two registers) is added to minimize context switching overhead during interrupt/exception process- ing. the register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. the execution unit includes: ? 32-bit adder used for calculating the data address ? address unit for calculating the next instruction address ? logic for branch determination and branch target address calculation ? load aligner ? bypass multiplexers used to avoid stalls when executing instruction streams where data producing instructions are followed closely by consumers of their results ? leading zero/one detect unit for implementing the clz and clo instructions ? arithmetic logic unit (alu) for performing bitwise logical operations ? shifter and store aligner 3.2.2 multiply/divide unit (mdu) the mips32 ? m4k ? processor core includes a multi- ply/divide unit (mdu) that co ntains a separate pipeline for multiply and divide operations. this pipeline oper- ates in parallel with the int eger unit (iu) pipeline and does not stall when the iu pipeline stalls. this allows mdu operations to be part ially masked by system stalls and/or other integer unit instructions. the high-performance mdu consists of a 32x16 booth recoded multiplier, result/accumulation registers (hi and lo), a divide state machine, and the necessary multiplexers and control logic. the first number shown (?32? of 32x16) represents the rs operand. the second number (?16? of 32x16) represents the rt operand. the pic32 core only checks the value of the latter ( rt) oper- and to determine how many times the operation must pass through the multiplier. the 16x16 and 32x16 operations pass through the multiplier once. a 32x32 operation passes through the multiplier twice. the mdu supports execution of one 16x16 or 32x16 multiply operation every clock cycle; 32x32 multiply operations can be issued every other clock cycle. appropriate interlocks are implemented to stall the issuance of back-to-back 32x32 multiply operations. the multiply operand size is automatically determined by logic built into the mdu. divide operations are implemented with a simple 1 bit per clock iterative algorith m. an early-in detection checks the sign extension of the dividend ( rs ) operand. if rs is 8 bits wide, 23 iterations are skipped. for a 16-bit wide rs , 15 iterations are skipped and for a 24-bit wide rs , 7 iterations are skipped. any attempt to issue a sub- sequent mdu instruction while a divide is still active causes an iu pipeline stall until the divide operation is completed. table 3-1 lists the repeat rate (peak issue rate of cycles until the operation can be reissued) and latency (num- ber of cycles until a result is available) for the pic32 core multiply and divide instructions. the approximate latency and repeat rates are listed in terms of pipeline clocks. table 3-1: mips32 ? m4k ? processor core high-performance integer multiply/divide unit latencies and repeat rates opcode operand size (mul rt ) (div rs ) latency repeat rate mult/multu, madd/maddu, msub/msubu 16 bits 1 1 32 bits 2 2 mul 16 bits 2 1 32 bits 3 2 div/divu 8 bits 12 11 16 bits 19 18 24 bits 26 25 32 bits 33 32 www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 35 pic32mx1xx/2xx the mips architecture defines that the result of a multiply or divide operation be placed in the hi and lo registers. using the move-from-hi ( mfhi ) and move- from-lo ( mflo ) instructions, these values can be transferred to the general purpose register file. in addition to the hi/lo targeted operations, the mips32 ? architecture also defines a multiply instruc- tion, mul , which places the least significant results in the primary register file instead of the hi/lo register pair. by avoiding the explicit mflo instruction required when using the lo register , and by supporting multiple destination registers, the thro ughput of multiply-inten- sive operations is increased. two other instructions, multiply-add ( madd ) and multiply-subtract ( msub ), are used to perform the multiply-accumulate and multiply-subtract operations. the madd instruction multiplies two numbers and then adds the product to the current contents of the hi and lo registers. similarly, the msub instruction multiplies two operands and then subtra cts the product from the hi and lo registers. the madd and msub operations are commonly used in dsp algorithms. 3.2.3 system control coprocessor (cp0) in the mips architecture, cp0 is responsible for the virtual-to-physical address translation, the exception control system, the processor?s diagnostics capability, the operating modes (kernel, user and debug) and whether interrupts are enabled or disabled. configura- tion information, such as presence of options like mips16e, is also available by accessing the cp0 registers, listed in ta b l e 3 - 2 . table 3-2: coprocessor 0 registers register number register name function 0-6 reserved reserved in the pic32mx1xx/2xx family core. 7 hwrena enables access via the rdhwr instruction to select ed hardware registers. 8 badvaddr (1) reports the address for the most recent address-related exception. 9 count (1) processor cycle count. 10 reserved reserved in the pic32mx1xx/2xx family core. 11 compare (1) timer interrupt control. 12 status (1) processor status and control. 12 intctl (1) interrupt system status and control. 12 srsctl (1) shadow register set status and control. 12 srsmap (1) provides mapping from vectored interrupt to a shadow set. 13 cause (1) cause of last general exception. 14 epc (1) program counter at last exception. 15 prid processor identification and revision. 15 ebase exception vector base register. 16 config configuration register. 16 config1 configuration register 1. 16 config2 configuration register 2. 16 config3 configuration register 3. 17-22 reserved reserved in the pic32mx1xx/2xx family core. 23 debug (2) debug control and exception status. 24 depc (2) program counter at last debug exception. 25-29 reserved reserved in the pic32mx1xx/2xx family core. 30 errorepc (1) program counter at last error. 31 desave (2) debug handler scratchpad register. note 1: registers used in exception processing. 2: registers used during debug. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 36 preliminary ? 2011-2012 microchip technology inc. coprocessor 0 also contains the logic for identifying and managing exceptions. exceptions can be caused by a variety of sources, including alignment errors in data, external events or program errors. table 3-3 lists the exception types in order of priority. table 3-3: mips32 ? m4k ? processor core exception types 3.3 power management the mips ? m4k ? processor core offers a number of power management features, including low-power design, active power management and power-down modes of operation. the core is a static design that supports slowing or halting the clocks, which reduces system power consumpti on during idle periods. 3.3.1 instruction-controlled power management the mechanism for invoking power-down mode is through execution of the wait instruction. for more information on power management, see section 25.0 ?power-saving features? . 3.4 ejtag debug support the mips ? m4k ? processor core provides for an enhanced jtag (ejtag) interf ace for use in the soft- ware debug of application and kernel code. in addition to standard user mode and kernel modes of operation, the m4k ? core provides a debug mode that is entered after a debug exception (derived from a hardware breakpoint, single-step exception, etc.) is taken and continues until a debug exception return ( deret ) instruction is executed. duri ng this time, the processor executes the debug exception handler routine. the ejtag interface operates through the test access port (tap), a serial communication port used for trans- ferring test data in and out of the core. in addition to the standard jtag instructio ns, special instructions defined in the ejtag spec ification define which registers are selected and how they are used. exception description reset assertion mclr or a power-on reset (por). dss ejtag debug single step. dint ejtag debug interrupt. caused by the assertion of the external ej_dint input or by setting the ejtagbrk bit in the ecr register. nmi assertion of nmi signal. interrupt assertion of unmasked hardware or software interrupt signal. dib ejtag debug hardware instruction break matched. adel fetch address alignment error. fetch reference to protected address. ibe instruction fetch bus error. dbp ejtag breakpoint (execution of sdbbp instruction). sys execution of syscall instruction. bp execution of break instruction. ri execution of a reserved instruction. cpu execution of a coprocessor instruction for a coprocessor that is not enabled. ceu execution of a corextend instruction when corextend is not enabled. ov execution of an arithmetic instruction that overflowed. tr execution of a trap (when trap condition is true). ddbl/ddbs ejtag data address break (address only) or ejtag data value break on store (address + value). adel load address alignment error. load reference to protected address. ades store address alignment error. store to protected address. dbe load or store bus error. ddbl ejtag data hardware breakpoint matched in load data compare. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 37 pic32mx1xx/2xx 4.0 memory organization pic32mx1xx/2xx microcontrollers provide 4 gb of unified virtual memory address space. all memory regions, including program, data memory, sfrs and configuration registers, reside in this address space at their respective unique addresses. the program and data memories can be optionally partitioned into user and kernel memories. in addition, the data memory can be made executable, al lowing pic32mx1xx/2xx devices to execute from data memory. key features include: ? 32-bit native data width ? separate user (kuseg) and kernel (kseg0/kseg1) mode address space ? flexible program flash memory partitioning ? flexible data ram partitioning for data and program space ? separate boot flash memory for protected code ? robust bus exception handling to intercept runaway code ? simple memory mapping with fixed mapping translation (fmt) unit ? cacheable (kseg0) and non-cacheable (kseg1) address regions 4.1 pic32mx1xx/2xx memory layout pic32mx1xx/2xx microcontr ollers implement two address schemes: virtual and physical. all hardware resources, such as prog ram memory, data memory and peripherals, are located at their respective physical addresses. virtual addresses are exclusively used by the cpu to fetch and execut e instructions as well as access peripherals. physica l addresses are used by bus master peripherals, such as dma and the flash controller, that access memory independently of the cpu. the memory maps for the pic32mx1xx/2xx devices are illustrated in figure 4-1 and figure 4-2 . note: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source.for detailed information, refer to section 3. ?memory organization? (ds61115) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 38 preliminary ? 2011-2012 microchip technology inc. figure 4-1: memory map on reset for pic32mx11x/21x devices (1) virtual memory map physical memory map 0xffffffff reserved reserved 0xffffffff 0xbfc00c00 0xbfc00bff device configuration registers 0xbfc00bf0 0xbfc00bef boot flash 0xbfc00000 reserved 0xbf900000 0xbf8fffff sfrs 0xbf800000 reserved 0xbd004000 0xbd003fff program flash (2) 0xbd000000 reserved 0xa0001000 0xa0000fff ram (2) 0xa0000000 0x1fc00c00 reserved device configuration registers 0x1fc00bff 0x9fc00c00 0x9fc00bff device configuration registers 0x1fc00bf0 boot flash 0x1fc00bef 0x9fc00bf0 0x9fc00bef boot flash 0x1fc00000 reserved 0x9fc00000 0x1f900000 reserved sfrs 0x1f8fffff 0x9d004000 0x1f800000 0x9d003fff program flash (2) reserved 0x9d000000 0x1d004000 reserved program flash (2) 0x1d003fff 0x80001000 0x80000fff ram (2) 0x1d000000 reserved 0x80000000 0x00001000 reserved ram (2) 0x00000fff 0x00000000 0x00000000 note 1: memory areas are not shown to scale. 2: the size of this memory region is programmable (see section 3. ?memory organization? (ds61115) in the ?pic32 family reference manual? ) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). kseg1 kseg0 www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 39 pic32mx1xx/2xx figure 4-2: memory map on reset for pic32mx12x/22x devices (1) virtual memory map physical memory map 0xffffffff reserved reserved 0xffffffff 0xbfc00c00 0xbfc00bff device configuration registers 0xbfc00bf0 0xbfc00bef boot flash 0xbfc00000 reserved 0xbf900000 0xbf8fffff sfrs 0xbf800000 reserved 0xbd008000 0xbd007fff program flash (2) 0xbd000000 reserved 0xa0002000 0xa0001fff ram (2) 0xa0000000 0x1fc00c00 reserved device configuration registers 0x1fc00bff 0x9fc00c00 0x9fc00bff device configuration registers 0x1fc00bf0 boot flash 0x1fc00bef 0x9fc00bf0 0x9fc00bef boot flash 0x1fc00000 reserved 0x9fc00000 0x1f900000 reserved sfrs 0x1f8fffff 0x9d008000 0x1f800000 0x9d007fff program flash (2) reserved 0x9d000000 0x1d008000 reserved program flash (2) 0x1d007fff 0x80002000 0x80001fff ram (2) 0x1d000000 reserved 0x80000000 0x00002000 reserved ram (2) 0x00001fff 0x00000000 0x00000000 note 1: memory areas are not shown to scale. 2: the size of this memory region is programmable (see section 3. ?memory organization? (ds61115) in the ?pic32 family reference manual? ) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). kseg1 kseg0 www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 40 preliminary ? 2011-2012 microchip technology inc. figure 4-3: memory map on reset for pic32mx13x/23x devices (1) virtual memory map physical memory map 0xffffffff reserved reserved 0xffffffff 0xbfc00c00 0xbfc00bff device configuration registers 0xbfc00bf0 0xbfc00bef boot flash 0xbfc00000 reserved 0xbf900000 0xbf8fffff sfrs 0xbf800000 reserved 0xbd010000 0xbd00ffff program flash (2) 0xbd000000 reserved 0xa0004000 0xa0003fff ram (2) 0xa0000000 0x1fc00c00 reserved device configuration registers 0x1fc00bff 0x9fc00c00 0x9fc00bff device configuration registers 0x1fc00bf0 boot flash 0x1fc00bef 0x9fc00bf0 0x9fc00bef boot flash 0x1fc00000 reserved 0x9fc00000 0x1f900000 reserved sfrs 0x1f8fffff 0x9d010000 0x1f800000 0x9d00ffff program flash (2) reserved 0x9d000000 0x1d010000 reserved program flash (2) 0x1d00ffff 0x80004000 0x80003fff ram (2) 0x1d000000 reserved 0x80000000 0x00004000 reserved ram (2) 0x00003fff 0x00000000 0x00000000 note 1: memory areas are not shown to scale. 2: the size of this memory region is programmable (see section 3. ?memory organization? (ds61115) in the ?pic32 family reference manual? ) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). kseg1 kseg0 www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 41 pic32mx1xx/2xx figure 4-4: memory map on reset for pic32mx15x/25x devices (1) virtual memory map physical memory map 0xffffffff reserved reserved 0xffffffff 0xbfc00c00 0xbfc00bff device configuration registers 0xbfc00bf0 0xbfc00bef boot flash 0xbfc00000 reserved 0xbf900000 0xbf8fffff sfrs 0xbf800000 reserved 0xbd020000 0xbd01ffff program flash (2) 0xbd000000 reserved 0xa0008000 0xa0007fff ram (2) 0xa0000000 0x1fc00c00 reserved device configuration registers 0x1fc00bff 0x9fc00c00 0x9fc00bff device configuration registers 0x1fc00bf0 boot flash 0x1fc00bef 0x9fc00bf0 0x9fc00bef boot flash 0x1fc00000 reserved 0x9fc00000 0x1f900000 reserved sfrs 0x1f8fffff 0x9d020000 0x1f800000 0x9d01ffff program flash (2) reserved 0x9d000000 0x1d020000 reserved program flash (2) 0x1d01ffff 0x80008000 0x80007fff ram (2) 0x1d000000 reserved 0x80000000 0x00008000 reserved ram (2) 0x00007fff 0x00000000 0x00000000 note 1: memory areas are not shown to scale. 2: the size of this memory region is programmable (see section 3. ?memory organization? (ds61115) in the ?pic32 family reference manual? ) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). kseg1 kseg0 www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 42 preliminary ? 2011-2012 microchip technology inc. 4.1.1 peripheral registers locations table 4-1 through ta b l e 4 - 2 7 contain the peripheral address maps for the pic32mx1xx/2xx devices. table 4-1: bus matrix register map virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2000 bmxcon (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? bmxerrixi bmxerricd bmxerrdma bmxerrds bmxerris 001f 15:0 ? ? ? ? ? ? ? ? ?bmxwsdrm ? ? ? bmxarb<2:0> 0041 2010 bmxdkpba (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 bmxdkpba<15:0> 0000 2020 bmxdudba (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 bmxdudba<15:0> 0000 2030 bmxdupba (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 bmxdupba<15:0> 0000 2040 bmxdrmsz 31:16 bmxdrmsz<31:0> xxxx 15:0 xxxx 2050 bmxpupba (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? bmxpupba<19:16> 0000 15:0 bmxpupba<15:0> 0000 2060 bmxpfmsz 31:16 bmxpfmsz<31:0> xxxx 15:0 xxxx 2070 bmxbootsz 31:16 bmxbootsz<31:0> 0000 15:0 3000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at it s virtual address, plus an offset of 0x4, 0x8 and 0xc, respecti vely. see section 11.2 ?clr, set and inv registers? for more information. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 43 pic32mx1xx/2xx table 4-2: interrupt register map (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 intcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ss0 0000 15:0 ? ? ? mvec ?tpc<2:0> ? ? ? int4ep int3ep int2ep int1ep int0ep 0000 1010 intstat (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ?sripl<2:0> ? ? vec<5:0> 0000 1020 iptmr 31:16 iptmr<31:0> 0000 15:0 0000 1030 ifs0 31:16 fceif rtccif fscmif ad1if oc5if ic5if ic5eif t5i f int4if oc4if ic4if ic4eif t4if int3if oc3if ic3if 0000 15:0 ic3eif t3if int2if oc2if ic2if ic2eif t2if int1 if oc1if ic1if ic1eif t1if int0if cs1if cs0if ctif 0000 1040 ifs1 31:16 dma3if dma2if dma1if dma0if ctmuif i2c2mif i2c2sif i2c2bif u2txif u2rxif u2eif spi2txif spi2rxif spi2eif pmpeif pmpif 0000 15:0 cncif cnbif cnaif i2c1mif i2c1sif i2c1bif u1txif u1rxif u1eif spi1txif spi1rxif spi1eif usbif (2) cmp3if cmp2if cmp1if 0000 1060 iec0 31:16 fceie rtccie fscmie ad1ie oc5ie ic5ie ic5eie t5i e int4ie oc4ie ic4ie ic4eie t4ie int3ie oc3ie ic3ie 0000 15:0 ic3eie t3ie int2ie oc2ie ic2ie ic2eie t2ie int1 ie oc1ie ic1ie ic1eie t1ie int0ie cs1ie cs0ie ctie 0000 1070 iec1 31:16 dma3ie dma2ie dma1ie dma0ie ctmuie i2c2mie i2c2sie i2c2b ie u2txie u2rxie u2eie spi2txie spi2rxie spi2eie pmpeie pmpie 0000 15:0 cncie cnbie cnaie i2c1mie i2c1sie i2c1bie u1txie u1rxie u1eie spi1txie spi1rxie spi1eie usbie (2) cmp3ie cmp2ie cmp1ie 0000 1090 ipc0 31:16 ? ? ? int0ip<2:0> int0is<1:0> ? ? ? cs1ip<2:0> cs1is<1:0> 0000 15:0 ? ? ? cs0ip<2:0> cs0is<1:0> ? ? ? ctip<2:0> ctis<1:0> 0000 10a0 ipc1 31:16 ? ? ? int1ip<2:0> int1is<1:0> ? ? ? oc1ip<2:0> oc1is<1:0> 0000 15:0 ? ? ? ic1ip<2:0> ic1is<1:0> ? ? ? t1ip<2:0> t1is<1:0> 0000 10b0 ipc2 31:16 ? ? ? int2ip<2:0> int2is<1:0> ? ? ? oc2ip<2:0> oc2is<1:0> 0000 15:0 ? ? ? ic2ip<2:0> ic2is<1:0> ? ? ? t2ip<2:0> t2is<1:0> 0000 10c0 ipc3 31:16 ? ? ? int3ip<2:0> int3is<1:0> ? ? ? oc3ip<2:0> oc3is<1:0> 0000 15:0 ? ? ? ic3ip<2:0> ic3is<1:0> ? ? ? t3ip<2:0> t3is<1:0> 0000 10d0 ipc4 31:16 ? ? ? int4ip<2:0> int4is<1:0> ? ? ? oc4ip<2:0> oc4is<1:0> 0000 15:0 ? ? ? ic4ip<2:0> ic4is<1:0> ? ? ? t4ip<2:0> t4is<1:0> 0000 10e0 ipc5 31:16 ? ? ? ad1ip<2:0> ad1is<1:0> ? ? ? oc5ip<2:0> oc5is<1:0> 0000 15:0 ? ? ? ic5ip<2:0> ic5is<1:0> ? ? ? t5ip<2:0> t5is<1:0> 0000 10f0 ipc6 31:16 ? ? ? cmp1ip<2:0> cmp1is<1:0> ? ? ? fceip<2:0> fceis<1:0> 0000 15:0 ? ? ? rtccip<2:0> rtccis<1:0> ? ? ? fscmip<2:0> fscmis<1:0> 0000 1100 ipc7 31:16 ? ? ? spi1ip<2:0> spi1is<1:0> ? ? ? usbip<2:0> (2) usbis<1:0> (2) 0000 15:0 ? ? ? cmp3ip<2:0> cmp3is<1:0> ? ? ? cmp2ip<2:0> cmp2is<1:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: with the exception of those noted, all regi sters in this table have corresponding clr, set and inv registers at their virtual a ddresses, plus offsets of 0x4 0x8 and 0xc, respectively. see section 11.2 ?clr, set and inv registers? for more information. 2: these bits are not availabl e on pic32mx1xx devices. 3: this register does not have associated clr, set, inv registers. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 44 preliminary ? 2011-2012 microchip technology inc. 1110 ipc8 31:16 ? ? ? pmpip<2:0> pmpis<1:0> ? ? ? cnip<2:0> cnis<1:0> 0000 15:0 ? ? ? i2c1ip<2:0> i2c1is<1:0> ? ? ? u1ip<2:0> u1is<1:0> 0000 1120 ipc9 31:16 ? ? ? ctmuip<2:0> ctmuis<1:0> ? ? ? i2c2ip<2:0> i2c2is<1:0> 0000 15:0 ? ? ? u2ip<2:0> u2is<1:0> ? ? ? spi2ip<2:0> spi2is<1:0> 0000 1130 ipc10 31:16 ? ? ? dma3ip<2:0> dma3is<1:0> ? ? ? dma2ip<2:0> dma2is<1:0> 0000 15:0 ? ? ? dma1ip<2:0> dma1is<1:0> ? ? ? dma0ip<2:0> dma0is<1:0> 0000 table 4-2: interrupt register map (1) (continued) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: with the exception of those noted, all regi sters in this table have corresponding clr, set and inv registers at their virtual a ddresses, plus offsets of 0x4 0x8 and 0xc, respectively. see section 11.2 ?clr, set and inv registers? for more information. 2: these bits are not availabl e on pic32mx1xx devices. 3: this register does not have associated clr, set, inv registers. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 45 pic32mx1xx/2xx table 4-3: timer1-timer5 register map (1) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0600 t1con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl twdis twip ? ? ?tgate ?tckps<1:0> ?tsynctcs ? 0000 0610 tmr1 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 tmr1<15:0> 0000 0620 pr1 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pr1<15:0> ffff 0800 t2con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? tgate tckps<2:0> t32 ?tcs ? 0000 0810 tmr2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 tmr2<15:0> 0000 0820 pr2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pr2<15:0> ffff 0a00 t3con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? tgate tckps<2:0> ? ?tcs ? 0000 0a10 tmr3 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 tmr3<15:0> 0000 0a20 pr3 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pr3<15:0> ffff 0c00 t4con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? tgate tckps<2:0> t32 ?tcs ? 0000 0c10 tmr4 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 tmr4<15:0> 0000 0c20 pr4 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pr4<15:0> ffff 0e00 t5con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? tgate tckps<2:0> ? ?tcs ? 0000 0e10 tmr5 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 tmr5<15:0> 0000 0e20 pr5 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pr5<15:0> ffff legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 11.2 ?clr, set and inv registers? for more information. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 46 preliminary ? 2011-2012 microchip technology inc. table 4-4: input capture 1-input capture 5 register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2000 ic1con (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2010 ic1buf 31:16 ic1buf<31:0> xxxx 15:0 xxxx 2200 ic2con (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2210 ic2buf 31:16 ic2buf<31:0> xxxx 15:0 xxxx 2400 ic3con (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2410 ic3buf 31:16 ic3buf<31:0> xxxx 15:0 xxxx 2600 ic4con (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2610 ic4buf 31:16 ic4buf<31:0> xxxx 15:0 xxxx 2800 ic5con (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2810 ic5buf 31:16 ic5buf<31:0> xxxx 15:0 xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at its virtual address, plus an offset of 0x4, 0x8 and 0xc, respecti vely. see section 11.2 ?clr, set and inv registers? for more information. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 47 pic32mx1xx/2xx table 4-5: output compare 1-output compare 5 register map (1) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3000 oc1con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? ? ? oc32 ocflt octsel ocm<2:0> 0000 3010 oc1r 31:16 oc1r<31:0> xxxx 15:0 xxxx 3020 oc1rs 31:16 oc1rs<31:0> xxxx 15:0 xxxx 3200 oc2con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? ? ? oc32 ocflt octsel ocm<2:0> 0000 3210 oc2r 31:16 oc2r<31:0> xxxx 15:0 xxxx 3220 oc2rs 31:16 oc2rs<31:0> xxxx 15:0 xxxx 3400 oc3con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? ? ? oc32 ocflt octsel ocm<2:0> 0000 3410 oc3r 31:16 oc3r<31:0> xxxx 15:0 xxxx 3420 oc3rs 31:16 15:0 oc3rs<31:0> xxxx xxxx 3600 oc4con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? ? ? oc32 ocflt octsel ocm<2:0> 0000 3610 oc4r 31:16 oc4r<31:0> xxxx 15:0 xxxx 3620 oc4rs 31:16 15:0 oc4rs<31:0> xxxx xxxx 3800 oc5con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? ? ? oc32 ocflt octsel ocm<2:0> 0000 3810 oc5r 31:16 oc5r<31:0> xxxx 15:0 xxxx 3820 oc5rs 31:16 oc5rs<31:0> xxxx 15:0 xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 11.2 ?clr, set and inv registers? for more information. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 48 preliminary ? 2011-2012 microchip technology inc. table 4-6: i2c1 and i2c2 register map (1) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5000 i2c1con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl sclrel strict a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 5010 i2c1stat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d/a p s r/w rbf tbf 0000 5020 i2c1add 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? address register 0000 5030 i2c1msk 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? address mask register 0000 5040 i2c1brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? baud rate generator register 0000 5050 i2c1trn 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? transmit register 0000 5060 i2c1rcv 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? receive register 0000 5100 i2c2con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl sclrel strict a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 5110 i2c2stat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d/a p s r/w rbf tbf 0000 5120 i2c2add 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? address register 0000 5130 i2c2msk 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? address mask register 0000 5140 i2c2brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? baud rate generator register 0000 5150 i2c2trn 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? transmit register 0000 5160 i2c2rcv 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? receive register 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table except i2cxrcv have corresponding cl r, set and inv registers at their virtual addresses, plus offse ts of 0x4, 0x8 and 0xc, respectively. see section 11.2 ?clr, set and inv registers? for more information. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 49 pic32mx1xx/2xx table 4-7: uart1 and uart2 register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6000 u1mode (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidlirenrtsmd ? uen<1:0> wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 6010 u1sta (1) 31:16 ? ? ? ? ? ? ? adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 6020 u1txreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? tx8 transmit register 0000 6030 u1rxreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? rx8 receive register 0000 6040 u1brg (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 baud rate generator prescaler 0000 6200 u2mode (1) 31:16 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 on ?sidlirenrtsmd ? uen<1:0> wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 6210 u2sta (1) 31:16 ? ? ? ? ? ? ? adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 6220 u2txreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? tx8 transmit register 0000 6230 u2rxreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? rx8 receive register 0000 6240 u2brg (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 baud rate generator prescaler 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at its virtual address, plus an offset of 0x4, 0x8 and 0xc, respecti vely. see section 11.2 ?clr, set and inv registers? for more information. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 50 preliminary ? 2011-2012 microchip technology inc. table 4-8: spi2 and spi2 register map (1) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5800 spi1con 31:16 frmen frmsync frmpol mssen frmsypw frmcnt<2:0> mclksel ? ? ? ? ? spife enhbuf 0000 15:0 on ? sidl dissdo mode32 mode16 smp cke ssen ckp msten dissdi stxisel<1:0> srxisel<1:0> 0000 5810 spi1stat 31:16 ? ? ? rxbufelm<4:0> ? ? ? txbufelm<4:0> 0000 15:0 ? ? ? frmerr spibusy ? ? spitur srmt spirov spirbe ?spitbe ?spitbfspirbf 0008 5820 spi1buf 31:16 data<31:0> 0000 15:0 0000 5830 spi1brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ?brg<8:0> 0000 5840 spi1con2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 spi sgnext ? ? frm erren spi roven spi turen ignrov igntur auden ? ? ? aud- mono ? audmod<1:0> 0000 5a00 spi2con 31:16 frmen frmsync frmpol mssen frmsypw frmcnt<2:0> mclksel ? ? ? ? ? spife enhbuf 0000 15:0 on ? sidl dissdo mode32 mode16 smp cke ssen ckp msten dissdi stxisel<1:0> srxisel<1:0> 0000 5a10 spi2stat 31:16 ? ? ? rxbufelm<4:0> ? ? ? txbufelm<4:0> 0000 15:0 ? ? ? frmerr spibusy ? ? spitur srmt spirov spirbe ?spitbe ?spitbfspirbf 0008 5a20 spi2buf 31:16 data<31:0> 0000 15:0 0000 5a30 spi2brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ?brg<8:0> 0000 5a40 spi2con2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 spi sgnext ? ? frm erren spi roven spi turen ignrov igntur auden ? ? ? aud mono ? audmod<1:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table except spixbuf have corresponding cl r, set and inv registers at their virtual addresses, plus offse ts of 0x4, 0x8 and 0xc, respectively. see section 11.2 ?clr, set and inv registers? for more information. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 51 pic32mx1xx/2xx table 4-9: adc register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 9000 ad1con1 (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? form<2:0> ssrc<2:0> clrasam ?asamsampdone 0000 9010 ad1con2 (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 vcfg<2:0> offcal ? cscna ? ?bufs ?smpi<3:0>bufmalts 0000 9020 ad1con3 (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 adrc ? ? samc<4:0> adcs<7:0> 0000 9040 ad1chs (1) 31:16 ch0nb ? ? ? ch0sb<3:0> ch0na ? ? ? ch0sa<3:0> 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 9050 ad1cssl (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cssl15 cssl14 cssl13 cssl12 cssl11 cssl10 cssl9 c ssl8 cssl7 cssl6 cssl5 cssl4 cssl3 cssl2 cssl1 cssl0 0000 9070 adc1buf0 31:16 adc result word 0 (adc1buf0<31:0>) 0000 15:0 0000 9080 adc1buf1 31:16 adc result word 1 (adc1buf1<31:0>) 0000 15:0 0000 9090 adc1buf2 31:16 adc result word 2 (adc1buf2<31:0>) 0000 15:0 0000 90a0 adc1buf3 31:16 adc result word 3 (adc1buf3<31:0>) 0000 15:0 0000 90b0 adc1buf4 31:16 adc result word 4 (adc1buf4<31:0>) 0000 15:0 0000 90c0 adc1buf5 31:16 adc result word 5 (adc1buf5<31:0>) 0000 15:0 0000 90d0 adc1buf6 31:16 adc result word 6 (adc1buf6<31:0>) 0000 15:0 0000 90e0 adc1buf7 31:16 adc result word 7 (adc1buf7<31:0>) 0000 15:0 0000 90f0 adc1buf8 31:16 adc result word 8 (adc1buf8<31:0>) 0000 15:0 0000 9100 adc1buf9 31:16 adc result word 9 (adc1buf9<31:0>) 0000 15:0 0000 9110 adc1bufa 31:16 adc result word a (adc1bufa<31:0>) 0000 15:0 0000 9120 adc1bufb 31:16 adc result word b (adc1bufb<31:0>) 0000 15:0 0000 9130 adc1bufc 31:16 adc result word c (adc1bufc<31:0>) 0000 15:0 0000 9140 adc1bufd 31:16 adc result word d (adc1bufd<31:0>) 0000 15:0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 11.2 ?clr, set and inv registers? for details. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 52 preliminary ? 2011-2012 microchip technology inc. 9150 adc1bufe 31:16 adc result word e (adc1bufe<31:0>) 0000 15:0 0000 9160 adc1buff 31:16 adc result word f (adc1buff<31:0>) 0000 15:0 0000 table 4-9: adc register map (continued) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 11.2 ?clr, set and inv registers? for details. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 53 pic32mx1xx/2xx table 4-10: dma global register map (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3000 dmacon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? ? suspend dmabusy ? ? ? ? ? ? ? ? ? ? ? 0000 3010 dmastat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rdwr dmach<2:0> (2) 0000 3020 dmaaddr 31:16 dmaaddr<31:0> 0000 15:0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv regi sters at its virtual address, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 11.2 ?clr, set and inv registers? for more information. table 4-11: dma crc register map (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3030 dcrccon 31:16 ? ? byto<1:0> wbo ? ?bito ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? plen<4:0> crcen crcapp crctyp ? ? crcch<2:0> 0000 3040 dcrcdata 31:16 dcrcdata<31:0> 0000 15:0 0000 3050 dcrcxor 31:16 dcrcxor<31:0> 0000 15:0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 11.2 ?clr, set and inv registers? for more information. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 54 preliminary ? 2011-2012 microchip technology inc. table 4-12: dma channels 0-3 register map (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3060 dch0con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chbusy ? ? ? ? ? ? chchns chen chaed chchn chaen ? chedet chpri<1:0> 0000 3070 dch0econ 31:16 ? ? ? ? ? ? ? ? chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ? ? ? ff00 3080 dch0int 31:16 ? ? ? ? ? ? ? ? chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 ? ? ? ? ? ? ? ? chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 3090 dch0ssa 31:16 chssa<31:0> 0000 15:0 0000 30a0 dch0dsa 31:16 chdsa<31:0> 0000 15:0 0000 30b0 dch0ssiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chssiz<15:0> 0000 30c0 dch0dsiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdsiz<15:0> 0000 30d0 dch0sptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chsptr<15:0> 0000 30e0 dch0dptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdptr<15:0> 0000 30f0 dch0csiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcsiz<15:0> 0000 3100 dch0cptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcptr<15:0> 0000 3110 dch0dat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? chpdat<7:0> 0000 3120 dch1con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chbusy ? ? ? ? ? ? chchns chen chaed chchn chaen ? chedet chpri<1:0> 0000 3130 dch1econ 31:16 ? ? ? ? ? ? ? ? chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ? ? ? ff00 3140 dch1int 31:16 ? ? ? ? ? ? ? ? chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 ? ? ? ? ? ? ? ? chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 3150 dch1ssa 31:16 chssa<31:0> 0000 15:0 0000 3160 dch1dsa 31:16 chdsa<31:0> 0000 15:0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 11.2 ?clr, set and inv registers? for more information. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 55 pic32mx1xx/2xx 3170 dch1ssiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chssiz<15:0> 0000 3180 dch1dsiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdsiz<15:0> 0000 3190 dch1sptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chsptr<15:0> 0000 31a0 dch1dptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdptr<15:0> 0000 31b0 dch1csiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcsiz<15:0> 0000 31c0 dch1cptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcptr<15:0> 0000 31d0 dch1dat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? chpdat<7:0> 0000 31e0 dch2con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chbusy ? ? ? ? ? ? chchns chen chaed chchn chaen ? chedet chpri<1:0> 0000 31f0 dch2econ 31:16 ? ? ? ? ? ? ? ? chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ? ? ? ff00 3200 dch2int 31:16 ? ? ? ? ? ? ? ? chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 ? ? ? ? ? ? ? ? chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 3210 dch2ssa 31:16 chssa<31:0> 0000 15:0 0000 3220 dch2dsa 31:16 chdsa<31:0> 0000 15:0 0000 3230 dch2ssiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chssiz<15:0> 0000 3240 dch2dsiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdsiz<15:0> 0000 3250 dch2sptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chsptr<15:0> 0000 3260 dch2dptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdptr<15:0> 0000 3270 dch2csiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcsiz<15:0> 0000 table 4-12: dma channels 0-3 register map (1) (continued) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 11.2 ?clr, set and inv registers? for more information. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 56 preliminary ? 2011-2012 microchip technology inc. 3280 dch2cptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcptr<15:0> 0000 3290 dch2dat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? chpdat<7:0> 0000 32a0 dch3con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chbusy ? ? ? ? ? ? chchns chen chaed chchn chaen ? chedet chpri<1:0> 0000 32b0 dch3econ 31:16 ? ? ? ? ? ? ? ? chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ? ? ? ff00 32c0 dch3int 31:16 ? ? ? ? ? ? ? ? chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 ? ? ? ? ? ? ? ? chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 32d0 dch3ssa 31:16 chssa<31:0> 0000 15:0 0000 32e0 dch3dsa 31:16 chdsa<31:0> 0000 15:0 0000 32f0 dch3ssiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chssiz<15:0> 0000 3300 dch3dsiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdsiz<15:0> 0000 3310 dch3sptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chsptr<15:0> 0000 3320 dch3dptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdptr<15:0> 0000 3330 dch3csiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcsiz<15:0> 0000 3340 dch3cptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcptr<15:0> 0000 3350 dch3dat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? chpdat<7:0> 0000 table 4-12: dma channels 0-3 register map (1) (continued) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 11.2 ?clr, set and inv registers? for more information. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 57 pic32mx1xx/2xx table 4-13: comparator register map (1) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 a000 cm1con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on coe cpol ? ? ? ?coutevpol<1:0> ? cref ? ? cch<1:0> 00c3 a010 cm2con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on coe cpol ? ? ? ?coutevpol<1:0> ? cref ? ? cch<1:0> 00c3 a020 cm3con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on coe cpol ? ? ? ?coutevpol<1:0> ? cref ? ? cch<1:0> 00c3 a060 cmstat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ?sidl ? ? ? ? ? ? ? ? ? ? c3out c2out c1out 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv r egisters at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 11.2 ?clr, set and inv registers? for more information. table 4-14: comparator voltage reference register map (1) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 9800 cvrcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? ? ? ? ? ? ? ? cvroe cvrr cvrss cvr<3:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv re gisters at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 11.2 ?clr, set and inv registers? for more information. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 58 preliminary ? 2011-2012 microchip technology inc. table 4-15: flash controller register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 f400 nvmcon (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 wr wren wrerr lvderr lvdstat ? ? ? ? ? ? ? nvmop<3:0> 0000 f410 nvmkey 31:16 nvmkey<31:0> 0000 15:0 0000 f420 nvmaddr (1) 31:16 nvmaddr<31:0> 0000 15:0 0000 f430 nvmdata 31:16 nvmdata<31:0> 0000 15:0 0000 f440 nvmsrc addr 31:16 nvmsrcaddr<31:0> 0000 15:0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at their virtual addresses, plus offs ets of 0x4, 0x8 and 0xc, respec tively. see section 11.2 ?clr, set and inv registers? for more information. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 59 pic32mx1xx/2xx table 4-16: system control register map (1) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 f000 osccon 31:16 ? ? pllodiv<2:0> frcdiv<2:0> ? soscrdy pbdivrdy pbdiv<1:0> pllmult<2:0> x1xx (2) 15:0 ? cosc<2:0> ? nosc<2:0> clklock ulock (4) slock slpen cf ufrcen (4) soscen oswen xxxx (2) f010 osctun 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ?tun<5:0> 0000 f020 refocon 31:16 ? rodiv<14:0> 0000 15:0 on ?sidl oerslp ? divswen active ? ? ? ? rosel<3:0> 0000 f030 refotrim 31:16 rotrim<8:0> ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 0000 wdtcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? ? ? ? ? ? ? ? swdtps<4:0> wdtwinen wdtclr 0000 f600 rcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? cmr vregs extr swr ? wdto sleep idle bor por xxxx (2) f610 rswrst 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?swrst 0000 f200 cfgcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ?iolockpmdlock ? ? ? ? ? ? ? ?jtagen ? ? tdoen 000b f230 syskey (3) 31:16 syskey<31:0> 0000 15:0 0000 f240 pmd1 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ?cvrmd ? ? ?ctmumd ? ? ? ? ? ? ?ad1md 0000 f250 pmd2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? cmp3md cmp2md cmp1md 0000 f260 pmd3 31:16 ? ? ? ? ? ? ? ? ? ? ? oc5md oc4md oc3md oc2md oc1md 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ic5md ic4md ic3md ic2md ic1md 0000 f270 pmd4 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? t5md t4md t3md t2md t1md 0000 f280 pmd5 31:16 ? ? ? ? ? ? ? usb1md ? ? ? ? ? ? i2c1md i2c1md 0000 15:0 ? ? ? ? ? ? spi2md spi1md ? ? ? ? ? ?u2mdu1md 0000 f290 pmd6 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pmpmd 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ?refomdrtccmd 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: with the exception of those noted, all registers in this table have corresponding clr, set and inv registers at their virtual a ddresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 11.2 ?clr, set and inv registers? for more information. 2: reset values are dependent on the devcfgx configuration bits and the type of reset. 3: this register does not have associated clr, set, inv registers. 4: this bit is available on pic32mx2xx devices only. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 60 preliminary ? 2011-2012 microchip technology inc. table 4-17: devcfg: device configuration word summary virtual address (bfc0_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2ff0 devcfg3 31:16 fvbusonid fusbidio iol1way pmdl1way ? ? ? ? ? ? ? ? ? ? ? ? xxxx 15:0 userid<15:0> xxxx 2ff4 devcfg2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? fpllodiv<2:0> xxxx 15:0 upllen (1) ? ? ? ? upllidiv<2:0> (1) ?fpllmul<2:0> ? fpllidiv<2:0> xxxx 2ff8 devcfg1 31:16 ? ? ? ? ? ? fwdtwinsz<1:0> fwdten windis ?wdtps<4:0> xxxx 15:0 fcksm<1:0> fpbdiv<1:0> ? osciofnc poscmod<1:0> ieso ? fsoscen ? ?fnosc<2:0> xxxx 2ffc devcfg0 31:16 ? ? ?cp ? ? ?bwp ? ? ? ? ? ? ? ? xxxx 15:0 pwp<5:0> ? ? ? ? ? icesel<1:0> jtagen debug<1:0> xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this bit is available on pic32mx2xx devices only. table 4-18: device and revision id summary (1) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 f220 devid 31:16 ver<3:0> devid<27:16> xxxx 15:0 devid<15:0> xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: reset values are dependent on the device variant. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 61 pic32mx1xx/2xx table 4-19: porta register map (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6000 ansela 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ansa1 ansa0 0003 6010 trisa 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ?trisa10 (2) trisa9 (2) trisa8 (2) trisa7 (2) ? ? trisa4 trisa3 tri sa2 trisa1 trisa0 079f 6020 porta 31:16 ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ?ra10 (2) ra9 (2) ra8 (2) ra7 (2) ? ? ra4 ra3 ra2 ra1 ra0 xxxx 6030 lata 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ?lata10 (2) lata9 (2) lata8 (2) lata7 (2) ? ? lata4 lata3 lata2 lata1 lata0 xxxx 6040 odca 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? odca10 (2) odca9 (2) odca8 (2) odca7 (2) ? ? ? ? ? ? ? 0000 6050 cnpua 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? cnpua10 (2) cnpua9 (2) cnpua8 (2) cnpua7 (2) ? ? cnpua4 cnpua3 cnpua2 cnpua1 cnpua0 0000 6060 cnpda 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? cnpda10 (2) cnpda9 (2) cnpda8 (2) cnpda7 (2) ? ? cnpda4 cnpda3 cnpda2 cnpda1 cnpda0 0000 6070 cncona 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 6080 cnena 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? cniea10 (2) cniea9 (2) cniea8 (2) cniea7 (2) ? ? cniea4 cniea3 cniea2 cniea1 cniea0 0000 6090 cnstata 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? cnstata10 (2) cnstata9 (2) cnstata8 (2) cnstata7 (2) ? ? cnstata4 cnstata3 cnstata2 cnstata1 cnstata0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 11.2 ?clr, set and inv registers? for more information. 2: this bit is available on 44-pin devices only. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 62 preliminary ? 2011-2012 microchip technology inc. table 4-20: portb register map virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6100 anselb 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ansb15 ansb14 ansb13 ansb12 (2) ? ? ? ? ? ? ? ? ansb3 ansb2 ansb1 ansb0 e00f 6110 trisb 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 trisb15 trisb14 trisb13 trisb12 (2) trisb11 trisb10 trisb9 trisb8 trisb7 trisb6 (2) trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 ffff 6120 portb 31:16 ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 rb15 rb14 rb13 rb12 (2) rb11 rb10 rb9 rb8 rb7 rc6 (2) rb5 rb4 rb3 rb2 rb1 rb0 xxxx 6130 latb 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 latb15 latb14 latb13 latb12 (2) latb11 latb10 latb9 latb8 latb7 latb6 (2) latb5 latb4 latb3 latb2 latb1 latb0 xxxx 6140 odcb 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? odcb11 odcb10 odcb9 odcb8 odcb7 odcb6 odcb5 odcb4 ? ? ? ? 0000 6150 cnpub 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cnpub15 cnpub14 cnpub13 cnpub12 (2) cnpub11 cnpub10 cnpub9 cnpub8 cnpub7 cnpub6 (2) cnpub5 cnpub4 cnpub3 cnpub2 cnpub1 cnpub0 0000 6160 cnpdb 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cnpdb15 cnpdb14 cnpdb13 cnpdb12 (2) cnpdb11 cnpdb10 cnpdb9 cnpdb8 cnpdb7 cnpdb6 (2) cnpdb5 cnpdb4 cnpdb3 cnpdb2 cnpdb1 cnpdb0 0000 6170 cnconb 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 6180 cnenb 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cnieb15 cnieb14 cnieb13 cnieb11 (2) cnieb11 cnieb10 cnieb9 cnieb8 cnieb7 cnieb6 (2) cnieb5 cnieb4 cnieb3 cnieb2 cnieb1 cnieb0 0000 6190 cnstatb 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cn statb15 cn statb14 cn statb13 cn statb12 (2) cn statb11 cn statb10 cn statb9 cn statb8 cn statb7 cn statb6 (2) cn statb5 cn statb4 cn statb3 cn statb2 cn statb1 cn statb0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 11.2 ?clr, set and inv registers? for more information. 2: this bit is not available on pic32mx2xx devices. the reset val ue for the trisb register when this bit is not available is 0x000 0efbf. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 63 pic32mx1xx/2xx table 4-21: portc register map (1,2) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6200 anselc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ansc3 ansc2 (3) ansc1 ansc0 000f 6210 trisc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? trisc9 trisc8 (3) trisc7 (3) trisc6 (3) trisc5 (3) trisc4 (3) trisc3 trisc2 (3) trisc1 trisc0 03ff 6220 portc 31:16 ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? rc9 rc8 (3) rc7 (3) rc6 (3) rc5 (3) rc4 (3) rc3 rc2 (3) rc1 rc0 xxxx 6230 latc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ?latc9latc8 (3) latc7 (3) latc6 (3) latc5 (3) latc4 (3) latc3 latc2 (3) latc1 latc0 xxxx 6240 odcc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? odcc9 odcc8 (3) odcc7 (3) odcc6 (3) odcc5 (3) odcc4 (3) ? ? ? ? 0000 6250 cnpuc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? cnpuc9 cnpuc8 (3) cnpuc7 (3) cnpuc6 (3) cnpuc5 (3) cnpuc4 (3) cnpuc3 cnpuc2 (3) cnpuc1 cnpuc0 0000 6260 cnpdc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? cnpdc9 cnpdc8 (3) cnpdc7 (3) cnpdc6 (3) cnpdc5 (3) cnpdc4 (3) cnpdc3 cnpdc2 (3) cnpdc1 cnpdc0 0000 6270 cnconc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 6280 cnenc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? cniec9 cniec8 (3) cniec7 (3) cniec6 (3) cniec5 (3) cniec4 (3) cniec3 cniec2 (3) cniec1 cniec0 0000 6290 cnstatc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? cnstatc9 cnstatc8 (3) cnstatc7 (3) cnstatc6 (3) cnstatc5 (3) cnstatc4 (3) cnstatc3 cnstatc2 (3) cnstatc1 cnstatc0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 11.2 ?clr, set and inv registers? for more information. 2: portc is not available on 28-pin devices. 3: this bit is available on 44-pin devices only. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 64 preliminary ? 2011-2012 microchip technology inc. table 4-22: peripheral pin select input register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 fa04 int1r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?int1r<3:0> 0000 fa08 int2r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?int2r<3:0> 0000 fa0c int3r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?int3r<3:0> 0000 fa10 int4r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?int4r<3:0> 0000 fa18 t2ckr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?t2ckr<3:0> 0000 fa1c t3ckr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?t3ckr<3:0> 0000 fa20 t4ckr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?t4ckr<3:0> 0000 fa24 t5ckr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?t5ckr<3:0> 0000 fa28 ic1r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?ic1r<3:0> 0000 fa2c ic2r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?ic2r<3:0> 0000 fa30 ic3r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?ic3r<3:0> 0000 fa34 ic4r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?ic4r<3:0> 0000 fa38 ic5r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?ic5r<3:0> 0000 fa48 ocfar 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?ocfar<3:0> 0000 fa4c ocfbr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?ocfbr<3:0> 0000 fa50 u1rxr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?u1rxr<3:0> 0000 www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 65 pic32mx1xx/2xx fa54 u1ctsr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? u1ctsr<3:0> 0000 fa58 u2rxr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?u2rxr<3:0> 0000 fa5c u2ctsr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? u2ctsr<3:0> 0000 fa84 sdi1r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?sdi1r<3:0> 0000 fa88 ss1r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ss1r<3:0> 0000 fa90 sdi2r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?sdi2r<3:0> 0000 fa94 ss2r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ss2r<3:0> 0000 fab8 refclkir 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? refclkir<3:0> 0000 table 4-22: peripheral pin select input register map (continued) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 66 preliminary ? 2011-2012 microchip technology inc. table 4-23: peripheral pin select output register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 fb00 rpa0r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpa0<3:0> 0000 fb04 rpa1r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpa1<3:0> 0000 fb08 rpa2r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpa2<3:0> 0000 fb0c rpa3r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpa3<3:0> 0000 fb10 rpa4r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpa4<3:0> 0000 fb20 rpa8r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpa8<3:0> 0000 fb24 rpa9r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpa9<3:0> 0000 fb2c rpb0r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb0<3:0> 0000 fb30 rpb1r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb1<3:0> 0000 fb34 rpb2r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb2<3:0> 0000 fb38 rpb3r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb3<3:0> 0000 fb3c rpb4r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb4<3:0> 0000 fb40 rpb5r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb5<3:0> 0000 fb44 rpb6r (2) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb6<3:0> 0000 fb48 rpb7r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb7<3:0> 0000 fb4c rpb8r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb8<3:0> 0000 note 1: this register is only av ailable on 44-pin devices. 2: this register is only ava ilable on pic32mx1xx devices. 3: this register is only availa ble on 36-pin and 44-pin devices. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 67 pic32mx1xx/2xx fb50 rpb9r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb9<3:0> 0000 fb54 rpb10r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb10<3:0> 0000 fb58 rpb11r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?rpb11<3:0> 0000 fb60 rpb13r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb13<3:0> 0000 fb64 rpb14r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb14<3:0> 0000 fb68 rpb15r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb15<3:0> 0000 fb6c rpc0r (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpc0<3:0> 0000 fb70 rpc1r (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpc1<3:0> 0000 fb74 rpc2r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpc2<3:0> 0000 fb78 rpc3r (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpc3<3:0> 0000 fb7c rpc4r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpc4<3:0> 0000 fb80 rpc5r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpc5<3:0> 0000 fb84 rpc6r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpc6<3:0> 0000 fb88 rpc7r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpc7<3:0> 0000 fb8c rpc8r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpc8<3:0> 0000 fb90 rpc9r (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpc9<3:0> 0000 table 4-23: peripheral pin select ou tput register map (continued) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 note 1: this register is only av ailable on 44-pin devices. 2: this register is only ava ilable on pic32mx1xx devices. 3: this register is only availa ble on 36-pin and 44-pin devices. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 68 preliminary ? 2011-2012 microchip technology inc. table 4-24: parallel mast er port register map (1) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 7000 pmcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl adrmux<1:0> pmpttl ptwren ptrden csf<1:0> alp ?cs1p ? wrsp rdsp 0000 7010 pmmode 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 busy irqm<1:0> incm<1:0> ? mode<1:0> waitb<1:0> waitm<3:0> waite<1:0> 0000 7020 pmaddr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? cs1 ? ? ? addr<10:0> 0000 7030 pmdout 31:16 dataout<31:0> 0000 15:0 0000 7040 pmdin 31:16 datain<31:0> 0000 15:0 0000 7050 pmaen 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? pten14 ? ? ? pten<10:0> 0000 7060 pmstat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ibf ibov ? ? ib3f ib2f ib1f ib0f obe obuf ? ? ob3e ob2e ob1e ob0e 008f legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 11.2 ?clr, set and inv registers? for more information. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 69 pic32mx1xx/2xx table 4-25: rtcc register map (1) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0200 rtccon 31:16 ? ? ? ? ? ? cal<9:0> 0000 15:0 on ?sidl ? ? ? ? ? rtsecsel rtcclkon ? ? rtcwren rtcsync halfsec rtcoe 0000 0210 rtcalrm 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 alrmen chime piv alrmsync amask<3:0> arpt<7:0> 0000 0220 rtctime 31:16 hr10<3:0> hr01<3:0> min10<3:0> min01<3:0> xxxx 15:0 sec10<3:0> sec01<3:0> ? ? ? ? ? ? ? ? xx00 0230 rtcdate 31:16 year10<3:0> year01<3:0> month10<3:0> month01<3:0> xxxx 15:0 day10<3:0> day01<3:0> ? ? ? ? wday01<3:0> xx00 0240 alrmtime 31:16 hr10<3:0> hr01<3:0> min10<3:0> min01<3:0> xxxx 15:0 sec10<3:0> sec01<3:0> ? ? ? ? ? ? ? ? xx00 0250 alrmdate 31:16 ? ? ? ? ? ? ? ? month10<3:0> month01<3:0> 00xx 15:0 day10<3:0> day01<3:0> ? ? ? ? wday01<3:0> xx0x legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at its virtual address, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 11.2 ?clr, set and inv registers? for more information. table 4-26: ctmu register map (1) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 a200 ctmucon 31:16 edg1mod edg1pol edg1sel<3:0> edg2stat edg1stat edg2mod edg2pol edg2sel<3:0> ? ? 0000 15:0 on ? ctmusidl tgen edgen edgseqen idissen cttrig itrim<5:0> irng<1:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv re gisters at its virtual address, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 11.2 ?clr, set and inv registers? for more information. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 70 preliminary ? 2011-2012 microchip technology inc. table 4-27: usb register map (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5040 u1otgir (2) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? idif t1msecif lstateif actvif sesvdif sesendif ? vbusvdif 0000 5050 u1otgie 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? idie t1msecie lstateie actvie sesvdie sesendie ? vbusvdie 0000 5060 u1otgstat (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ?id ?lstate ? sesvd sesend ? vbusvd 0000 5070 u1otgcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? dppulup dmpulup dppuldwn dmpuldwn vbuson otgen vbuschg vbusdis 0000 5080 u1pwrc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ?uactpnd (4) ? ? uslpgrd usbbusy ? ususpend usbpwr 0000 5200 u1ir (2) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? stallif attachif resumeif idleif trnif sofif uerrif urstif 0000 detachif 0000 5210 u1ie 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? stallie attachie resumeie idleie trnie sofie uerrie urstie 0000 detachie 0000 5220 u1eir (2) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? btsef bmxef dmaef btoef dfn8ef crc16ef crc5ef pidef 0000 eofef 0000 5230 u1eie 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? btsee bmxee dmaee btoee dfn8ee crc16ee crc5ee pidee 0000 eofee 0000 5240 u1stat (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? endpt<3:0> dir ppbi ? ? 0000 5250 u1con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? jstate se0 pktdis usbrst hosten resume ppbrst usben 0000 tokbusy sofen 0000 5260 u1addr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? lspden devaddr<6:0> 0000 5270 u1bdtp1 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? bdtptrl<7:1> ? 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: with the exception of those noted, all registers in this tabl e (except as noted) have corresponding clr, set and inv registers at its virtual address, plus an offset of 0x4, 0x8 and 0xc respectively. see section 11.2 ?clr, set and inv registers? for more information. 2: this register does not have associated set and inv registers. 3: this register does not have associ ated clr, set and inv registers. 4: reset value for this bit is undefined. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 71 pic32mx1xx/2xx 5280 u1frml (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? frml<7:0> 0000 5290 u1frmh (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? frmh<2:0> 0000 52a0 u1tok 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? pid<3:0> ep<3:0> 0000 52b0 u1sof 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? cnt<7:0> 0000 52c0 u1bdtp2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? bdtptrh<7:0> 0000 52d0 u1bdtp3 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? bdtptru<7:0> 0000 52e0 u1cnfg1 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ?uteyeuoemon ? usbsidl ? ? ? uasuspnd 0001 5300 u1ep0 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? lspd retrydis ? epcondis eprxen eptxen epstall ephshk 0000 5310 u1ep1 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5320 u1ep2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5330 u1ep3 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5340 u1ep4 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5350 u1ep5 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5360 u1ep6 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5370 u1ep7 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5380 u1ep8 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 table 4-27: usb register map (1) (continued) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: with the exception of those noted, all registers in this tabl e (except as noted) have corresponding clr, set and inv registers at its virtual address, plus an offset of 0x4, 0x8 and 0xc respectively. see section 11.2 ?clr, set and inv registers? for more information. 2: this register does not have associated set and inv registers. 3: this register does not have associ ated clr, set and inv registers. 4: reset value for this bit is undefined. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 72 preliminary ? 2011-2012 microchip technology inc. 5390 u1ep9 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 53a0 u1ep10 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 53b0 u1ep11 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 53c0 u1ep12 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 53d0 u1ep13 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 53e0 u1ep14 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 53f0 u1ep15 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 table 4-27: usb register map (1) (continued) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: with the exception of those noted, all registers in this tabl e (except as noted) have corresponding clr, set and inv registers at its virtual address, plus an offset of 0x4, 0x8 and 0xc respectively. see section 11.2 ?clr, set and inv registers? for more information. 2: this register does not have associated set and inv registers. 3: this register does not have associ ated clr, set and inv registers. 4: reset value for this bit is undefined. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 73 pic32mx1xx/2xx 4.2 control registers register 4-1 through register 4-8 are used for setting the ram and flash memory partitions for data and code. register 4-1: bmxcon: bus ma trix configuration register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? bmx errixi bmx erricd bmx errdma bmx errds bmx erris 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 r/w-1 u-0 u-0 u-0 r/w-0 r/w-0 r/w-1 ? bmx wsdrm ? ? ? bmxarb<2:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared bit 31-21 unimplemented: read as ? 0 ? bit 20 bmxerrixi: enable bus error from ixi bit 1 = enable bus error exceptions for unmapped address accesses initiated from ixi shared bus 0 = disable bus error exceptions for unmapped address accesses initiated from ixi shared bus bit 19 bmxerricd: enable bus error from icd debug unit bit 1 = enable bus error exceptions for unmapped address accesses initiated from icd 0 = disable bus error exceptions for unmapped address accesses initiated from icd bit 18 bmxerrdma: bus error from dma bit 1 = enable bus error exceptions for unmapped address accesses initiated from dma 0 = disable bus error exceptions for unmapped address accesses initiated from dma bit 17 bmxerrds: bus error from cpu data access bit (disabled in debug mode) 1 = enable bus error exceptions for unmapped address accesses initiated from cpu data access 0 = disable bus error exceptions for unmapped address accesses initiated from cpu data access bit 16 bmxerris: bus error from cpu instruction access bit (disabled in debug mode) 1 = enable bus error exceptions for unmapped addre ss accesses initiated from cpu instruction access 0 = disable bus error exceptions for unmapped addre ss accesses initiated from cpu instruction access bit 15-7 unimplemented: read as ? 0 ? bit 6 bmxwsdrm: cpu instruction or data access from data ram wait state bit 1 = data ram accesses from cpu have one wait state for address setup 0 = data ram accesses from cpu have zero wait states for address setup bit 5-3 unimplemented: read as ? 0 ? bit 2-0 bmxarb<2:0>: bus matrix arbitration mode bits 111 = reserved (using these configuration modes will produce undefined behavior) ? ? ? 011 = reserved (using these configuration modes will produce undefined behavior) 010 = arbitration mode 2 001 = arbitration mode 1 (default) 000 = arbitration mode 0 www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 74 preliminary ? 2011-2012 microchip technology inc. register 4-2: bmxdkpba: data ram ke rnel program base address register (1,2) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 bmxdkpba<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bmxdkpba<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-11 bmxdkpba<15:10>: drm kernel program base address bits when non-zero, this value selects the relative base address for kernel program space in ram bit 10-0 bmxdkpba<9:0>: read-only bits value is always ? 0 ?, which forces 1 kb increments note 1: at reset, the value in this register is forced to zero, which causes all of the ram to be allocated to kernal mode data usage. 2: the value in this register must be less than or equal to bmxdrmsz. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 75 pic32mx1xx/2xx register 4-3: bmxdudba: data ram user data base address register (1,2) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 bmxdudba<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bmxdudba<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-11 bmxdudba<15:10>: drm user data base address bits when non-zero, the value selects the relative base a ddress for user mode data space in ram, the value must be greater than bmxdkpba. bit 10-0 bmxdudba<9:0>: read-only bits value is always ? 0 ?, which forces 1 kb increments note 1: at reset, the value in this register is forced to zero, which causes all of the ram to be allocated to kernal mode data usage. 2: the value in this register must be less than or equal to bmxdrmsz. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 76 preliminary ? 2011-2012 microchip technology inc. register 4-4: bmxdupba: data ram user program base address register (1,2) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 bmxdupba<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bmxdupba<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-11 bmxdupba<15:10>: drm user program base address bits when non-zero, the value selects the relative base address for user mode program space in ram, bmxdupba must be greater than bmxdudba. bit 10-0 bmxdupba<9:0>: read-only bits value is always ? 0 ?, which forces 1 kb increments note 1: at reset, the value in this register is forced to zero, which causes all of the ram to be allocated to kernal mode data usage. 2: the value in this register must be less than or equal to bmxdrmsz. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 77 pic32mx1xx/2xx register 4-5: bmxdrmsz: data ram size register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 rrrrr r r r bmxdrmsz<31:24> 23:16 rrrrr r r r bmxdrmsz<23:16> 15:8 rrrrr r r r bmxdrmsz<15:8> 7:0 rrrrr r r r bmxdrmsz<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 bmxdrmsz<31:0>: data ram memory (drm) size bits static value that indicates the size of the data ram in bytes: 0x00001000 = device has 4 kb ram 0x00002000 = device has 8 kb ram 0x00004000 = device has 16 kb ram 0x00008000 = device has 32 kb ram register 4-6: bmxpupba: program fla sh (pfm) user program base address register (1,2) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? bmxpupba<19:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-0 bmxpupba<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bmxpupba<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-20 unimplemented: read as ? 0 ? bit 19-11 bmxpupba<19:11>: program flash (pfm) user program base address bits bit 10-0 bmxpupba<10:0>: read-only bits value is always ? 0 ?, which forces 2 kb increments note 1: at reset, the value in this register is forced to zero, which causes all of the ram to be allocated to kernal mode data usage. 2: the value in this register must be less than or equal to bmxpfmsz. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 78 preliminary ? 2011-2012 microchip technology inc. register 4-7: bmxpfmsz: program flash (pfm) size register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 rrrrr r r r bmxpfmsz<31:24> 23:16 rrrrr r r r bmxpfmsz<23:16> 15:8 rrrrr r r r bmxpfmsz<15:8> 7:0 rrrrr r r r bmxpfmsz<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 bmxpfmsz<31:0>: program flash memory (pfm) size bits static value that indicates the size of the pfm in bytes: 0x00004000 = device has 16 kb flash 0x00008000 = device has 32 kb flash 0x00010000 = device has 64 kb flash 0x00020000 = device has 128 kb flash register 4-8: bmxbootsz: boot flash (ifm) size register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 rrrrr r r r bmxbootsz<31:24> 23:16 rrrrr r r r bmxbootsz<23:16> 15:8 rrrrr r r r bmxbootsz<15:8> 7:0 rrrrr r r r bmxbootsz<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 bmxbootsz<31:0>: boot flash memory (bfm) size bits static value that indicates the size of the boot pfm in bytes: 0x00000c00 = device has 3 kb boot flash www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 79 pic32mx1xx/2xx 5.0 flash program memory pic32mx1xx/2xx devices contain an internal flash program memory for execut ing user code. there are three methods by which the user can program this memory: 1. run-time self-programming (rtsp) 2. ejtag programming 3. in-circuit serial programming? (icsp?) rtsp is performed by software executing from either flash or ram memory. information about rtsp techniques is available in section 5. ?flash program memory? (ds61121) in the ?pic32 family reference manual?. ejtag is performed using the ejtag port of the device and an ejtag capable programmer. icsp is performed using a serial data connection to the device and allows much faster programming times than rtsp. the ejtag and icsp methods are described in the ? pic32 flash programming specification ? (ds61145), which can be downloaded from the microchip web site. note 1: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 5. ?flash program memory? (ds61121) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 80 preliminary ? 2011-2012 microchip technology inc. register 5-1: nvmcon: programming control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r-0 r-0 r-0 u-0 u-0 u-0 wr wren wrerr (1) lvderr (1) lvdstat (1) ? ? ? 7:0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? nvmop<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 wr: write control bit this bit is writable when wren = 1 and the unlock sequence is followed. 1 = initiate a flash operation. hardware clears this bit when the operation completes 0 = flash operation complete or inactive bit 14 wren: write enable bit 1 = enable writes to wr bit and enables lvd circuit 0 = disable writes to wr bit and disables lvd circuit this is the only bit in this re gister reset by a device reset. bit 13 wrerr: write error bit (1) this bit is read-only and is automatically set by hardware. 1 = program or erase sequence did not complete successfully 0 = program or erase sequence completed normally bit 12 lvderr: low-voltage detect error bit (lvd circuit must be enabled) (1) this bit is read-only and is automatically set by hardware. 1 = low-voltage detected (possible data corruption, if wrerr is set) 0 = voltage level is acceptable for programming bit 11 lvdstat: low-voltage detect status bit (lvd circuit must be enabled) (1) this bit is read-only and is automatic ally set, and cleared, by hardware. 1 = low-voltage event active 0 = low-voltage event not active bit 10-4 unimplemented: read as ? 0 ? bit 3-0 nvmop<3:0>: nvm operation bits these bits are writable when wren = 0 . 1111 = reserved ? ? ? 0111 = reserved 0110 = no operation 0101 = program flash (pfm) erase operation: erases pfm, if all pages are not write-protected 0100 = page erase operation: erases page selected by nvmaddr, if it is not write-protected 0011 = row program operation: programs row select ed by nvmaddr, if it is not write-protected 0010 = no operation 0001 = word program operation: programs word selected by nvmaddr, if it is not write-protected 0000 = no operation note 1: this bit is cleared by setting nvmop == 0000b , and initiating a flash operation (i.e., wr). www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 81 pic32mx1xx/2xx register 5-2: nvmkey: programming unlock register (1) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 nvmkey<31:24> 23:16 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 nvmkey<23:16> 15:8 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 nvmkey<15:8> 7:0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 nvmkey<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 nvmkey<31:0>: unlock register bits these bits are write-only, and read as ? 0 ? on any read note 1: this register is used as part of the unlock se quence to prevent inadvertent writes to the pfm. register 5-3: nvmaddr: flash address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmaddr<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmaddr<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmaddr<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmaddr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 nvmaddr<31:0>: flash address bits bulk/chip/pfm erase: address is ignored. page erase: address identifies the page to erase. row program: address identifies the row to program. word program: address identifies the word to program. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 82 preliminary ? 2011-2012 microchip technology inc. register 5-4: nvmdata: flash program data register (1) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmdata<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmdata<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmdata<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmdata<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 nvmdata<31:0>: flash programming data bits note 1: the bits in this register are only reset by a power-on reset (por). register 5-5: nvmsrcaddr: source data address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmsrcaddr<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmsrcaddr<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmsrcaddr<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmsrcaddr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 nvmsrcaddr<31:0>: source data address bits the system physical address of th e data to be programmed into the flash when the nvmop<3:0> bits (nvmcon<3:0>) are set to perform row programming. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 83 pic32mx1xx/2xx 6.0 resets the reset module combines all reset sources and controls the device master reset signal, sysrst. the following is a list of device reset sources: ? por: power-on reset ?mclr : master clear reset pin ? swr: software reset ? wdtr: watchdog timer reset ? bor: brown-out reset ? cmr: configuration mismatch reset a simplified block diagram of the reset module is illustrated in figure 6-1 . figure 6-1: system reset block diagram note 1: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 7. ?resets? (ds61118) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. mclr v dd v dd rise detect por sleep or idle brown-out reset wdt time-out glitch filter bor configuration sysrst software reset power-up timer voltage enabled reset wdtr swr cmr mclr mismatch regulator www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 84 preliminary ? 2011-2012 microchip technology inc. register 6-1: rcon: re set control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0, hs r/w-0 ? ? ? ? ? ? cmr vregs 7:0 r/w-0, hs r/w-0, hs u-0 r/w-0, hs r/w- 0, hs r/w-0, hs r/w-1, hs r/w-1, hs extr swr ? wdto sleep idle bor (1) por (1) legend: hs = set by hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-10 unimplemented: read as ? 0 ? bit 9 cmr: configuration mismatch reset flag bit 1 = configuration mismatch reset has occurred 0 = configuration mismatch reset has not occurred bit 8 vregs: voltage regulator standby enable bit 1 = regulator is enabled and is on during sleep mode 0 = regulator is disabled and is off during sleep mode bit 7 extr: external reset (mclr ) pin flag bit 1 = master clear (pin) reset has occurred 0 = master clear (pin) reset has not occurred bit 6 swr: software reset flag bit 1 = software reset was executed 0 = software reset as not executed bit 5 unimplemented: read as ? 0 ? bit 4 wdto: watchdog timer time-out flag bit 1 = wdt time-out has occurred 0 = wdt time-out has not occurred bit 3 sleep: wake from sleep flag bit 1 = device was in sleep mode 0 = device was not in sleep mode bit 2 idle: wake from idle flag bit 1 = device was in idle mode 0 = device was not in idle mode bit 1 bor: brown-out reset flag bit (1) 1 = brown-out reset has occurred 0 = brown-out reset has not occurred bit 0 por: power-on reset flag bit (1) 1 = power-on rese t has occurred 0 = power-on reset has not occurred note 1: user software must clear this bit to view next detection. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 85 pic32mx1xx/2xx register 6-2: rswrst: software reset register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 w-0, hc ? ? ? ? ? ? ?swrst (1) legend: hc = cleared by hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-1 unimplemented: read as ? 0 ? bit 0 swrst: software reset trigger bit (1) 1 = enable software reset event 0 = no effect note 1: the system unlock sequence must be performed be fore the swrst bit can be written. refer to section 6. ?oscillator? (ds61112) in the ?pic32 family reference manual? for details. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 86 preliminary ? 2011-2012 microchip technology inc. notes: www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 87 pic32mx1xx/2xx 7.0 interrupt controller pic32mx1xx/2xx devices generate interrupt requests in response to interrupt events from peripheral modules. the interrupt control module ex ists externally to the cpu logic and prioritizes the interrupt events before presenting them to the cpu. the pic32mx1xx/2xx interrupt module includes the following features: ? up to 64 interrupt sources ? up to 44 interrupt vectors ? single and multi-vector mode operations ? five external interrupts with edge polarity control ? interrupt proximity timer ? seven user-selectable priority levels for each vector ? four user-selectable subpriority levels within each priority ? dedicated shadow set for all priority levels (1) ? software can generate any interrupt ? user-configurable interrupt vector table location ? user-configurable interrupt vector spacing figure 7-1: interrupt controller module block diagram note 1: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 8. ?interrupt controller? (ds61108) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: on pic32mx1xx/2xx devices, the dedicated shadow set is not present. interrupt controller interrupt requests vector number cpu core priority level www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 88 preliminary ? 2011-2012 microchip technology inc. table 7-1: interrupt irq, vector and bit location interrupt source (1) irq # vector # interrupt bit location persistent interrupt flag enable priori ty sub-priority highest natural order priority ct ? core timer interrupt 0 0 ifs0<0> iec0<0> ipc0<4:2> ipc0<1:0> no cs0 ? core software interrupt 0 1 1 ifs0<1> iec0<1> ipc0<12:10> ipc0<9:8> no cs1 ? core software interrupt 1 2 2 ifs0<2> iec0<2> ipc0<20:18> ipc0<17:16> no int0 ? external interrupt 3 3 ifs0<3> iec0<3> ipc0<28:26> ipc0<25:24> no t1 ? timer1 4 4 ifs0<4> iec0<4> ipc1<4:2> ipc1<1:0> no ic1e ? input capture 1 error 5 5 ifs0<5> iec0<5> ipc1<12:10> ipc1<9:8> yes ic1 ? input capture 1 6 5 ifs0<6> iec0<6> ipc1<12:10> ipc1<9:8> yes oc1 ? output compare 1 7 6 ifs0<7> iec0<7> ipc1<20:18> ipc1<17:16> no int1 ? external interrupt 1 8 7 ifs0<8> iec0<8> ipc1<28:26> ipc1<25:24> no t2 ? timer2 9 8 ifs0<9> iec0<9> ipc2<4:2> ipc2<1:0> no ic2e ? input capture 2 10 9 ifs0<10> iec0<10> ipc2<12:10> ipc2<9:8> yes ic2 ? input capture 2 11 9 ifs0<11> iec0<11> ipc2<12:10> ipc2<9:8> yes oc2 ? output compare 2 12 10 ifs0<12> iec0<12> ipc2<20:18> ipc2<17:16> no int2 ? external interrupt 2 13 11 ifs0<13> iec0<13> ipc2<28:26> ipc2<25:24> no t3 ? timer3 14 12 ifs0<14> iec0<14> ipc3<4:2> ipc3<1:0> no ic3e ? input capture 3 15 13 ifs0<15> iec0<15> ipc3<12:10> ipc3<9:8> yes ic3 ? input capture 3 16 13 ifs0<16> iec0<16> ipc3<12:10> ipc3<9:8> yes oc3 ? output compare 3 17 14 ifs0<17> iec0<17> ipc3<20:18> ipc3<17:16> no int3 ? external interrupt 3 18 15 ifs0<18> iec0<18> ipc3<28:26> ipc3<25:24> no t4 ? timer4 19 16 ifs0<19> iec0<19> ipc4<4:2> ipc4<1:0> no ic4e ? input capture 4 error 20 17 ifs0<20> iec0<20> ipc4<12:10> ipc4<9:8> yes ic4 ? input capture 4 21 17 ifs0<21> iec0<21> ipc4<12:10> ipc4<9:8> yes oc4 ? output compare 4 22 18 ifs0<22> iec0<22> ipc4<20:18> ipc4<17:16> no int4 ? external interrupt 4 23 19 ifs0<23> iec0<23> ipc4<28:26> ipc4<25:24> no t5 ? timer5 24 20 ifs0<24> iec0<24> ipc5<4:2> ipc5<1:0> no ic5e ? input capture 5 error 25 21 ifs0<25> iec0<25> ipc5<12:10> ipc5<9:8> yes ic5 ? input capture 5 26 21 ifs0<26> iec0<26> ipc5<12:10> ipc5<9:8> yes oc5 ? output compare 5 27 22 ifs0<27> iec0<27> ipc5<20:18> ipc5<17:16> no ad1 ? adc1 convert done 28 23 ifs0<28> iec0<28> ipc5<28:26> ipc5<25:24> yes fscm ? fail-safe clock monitor 29 24 ifs0<29> iec0<29> ipc6<4:2> ipc6<1:0> no rtcc ? real-time clock and calendar 30 25 ifs0<30> iec0<30> ipc6<12:10> ipc6<9:8> no fce ? flash control event 31 26 ifs0<31> iec0<31> ipc6<20:18> ipc6<17:16> no cmp1 ? comparator interrupt 32 27 ifs1<0> iec1<0> ipc6<28:26> ipc6<25:24> no cmp2 ? comparator interrupt 33 28 ifs1<1> iec1<1> ipc7<4:2> ipc7<1:0> no cmp3 ? comparator interrupt 34 29 ifs1<2> iec1<2> ipc7<12:10> ipc7<9:8> no usb ? usb interrupts 35 30 ifs1<3> iec1<3> ipc7<20:18> ipc7<17:16> yes spi1e ? spi1 fault 36 31 ifs1<4> iec1<4> ipc7<28:26> ipc7<25:24> yes spi1rx ? spi1 receive done 37 31 ifs1<5> iec1<5> ipc7<28:26> ipc7<25:24> yes spi1tx ? spi1 transfer done 38 31 ifs1<6> iec1<6> ipc7<28:26> ipc7<25:24> yes note 1: not all interrupt sources are available on all devices. see table 1: ?pic32mx1xx general purpose family features? and table 2: ?pic32mx2xx usb family features? for the lists of available peripherals. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 89 pic32mx1xx/2xx u1e ? uart1 fault 39 32 ifs1<7> iec1<7> ipc8<4:2> ipc8<1:0> yes u1rx ? uart1 receive done 40 32 ifs1<8> iec1<8> ipc8<4:2> ipc8<1:0> yes u1tx ? uart1 transfer done 41 32 ifs1<9> iec1<9> ipc8<4:2> ipc8<1:0> yes i2c1b ? i2c1 bus collision event 42 33 ifs1<10> iec1<10> ipc8<12:10> ipc8<9:8> yes i2c1s ? i2c1 slave event 43 33 ifs1<11> iec1<11> ipc8<12:10> ipc8<9:8> yes i2c1m ? i2c1 master event 44 33 ifs1<12> iec1<12> ipc8<12:10> ipc8<9:8> yes cna ? porta input change interrupt 45 34 ifs1<13> iec1<13> ipc8<20:18> ipc8<17:16> yes cnb ? portb input change interrupt 46 34 ifs1<14> iec1<14> ipc8<20:18> ipc8<17:16> yes cnc ? portc input change interrupt 47 34 ifs1<15> iec1<15> ipc8<20:18> ipc8<17:16> yes pmp ? parallel master port 48 35 ifs1<16> iec1<16> ipc8<28:26> ipc8<25:24> yes pmpe ? parallel master port error 49 35 i fs1<17> iec1<17> ipc8<28:26> ipc8<25:24> yes spi2e ? spi2 fault 50 36 ifs1<18> iec1<18> ipc9<4:2> ipc9<1:0> yes spi2rx ? spi2 receive done 51 36 ifs1<19> iec1<19> ipc9<4:2> ipc9<1:0> yes spi2tx ? spi2 transfer done 52 36 ifs1<20> iec1<20> ipc9<4:2> ipc9<1:0> yes u2e ? uart2 error 53 37 ifs1<21> iec1<21> ipc9<12:10> ipc9<9:8> yes u2rx ? uart2 receiver 54 37 ifs1<22> iec1<22> ipc9<12:10> ipc9<9:8> yes u2tx ? uart2 transmitter 55 37 ifs1<23> iec1<23> ipc9<12:10> ipc9<9:8> yes i2c2b ? i2c2 bus collision event 56 38 ifs 1<24> iec1<24> ipc9<20:18> ipc9<17:16> yes i2c2s ? i2c2 slave event 57 38 ifs1<25> iec1<25> ipc9<20:18> ipc9<17:16> yes i2c2m ? i2c2 master event 58 38 ifs1<26> iec1<26> ipc9<20:18> ipc9<17:16> yes ctmu ? ctmu event 59 39 ifs1<27> iec1<27> ipc9<28:26> ipc9<25:24> yes dma0 ? dma channel 0 60 40 ifs1<28> iec1<28> ipc10<4:2> ipc10<1:0> no dma1 ? dma channel 1 61 41 ifs1<29> iec1<29> ipc10<12:10> ipc10<9:8> no dma2 ? dma channel 2 62 42 ifs1<30> iec1<30> ipc10<20:18> ipc10<17:16> no dma3 ? dma channel 3 63 43 ifs1<31> iec1<31> ipc10<28:26> ipc10<25:24> no lowest natural order priority table 7-1: interrupt irq, vector and bit location (continued) interrupt source (1) irq # vector # interrupt bit location persistent interrupt flag enable priori ty sub-priority note 1: not all interrupt sources are available on all devices. see table 1: ?pic32mx1xx general purpose family features? and table 2: ?pic32mx2xx usb family features? for the lists of available peripherals. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 90 preliminary ? 2011-2012 microchip technology inc. register 7-1: intcon: interrupt control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ?ss0 15:8 u-0 u-0 u-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? mvec ?tpc<2:0> 7:0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? int4ep int3ep int2ep int1ep int0ep legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-17 unimplemented: read as ? 0 ? bit 16 ss0: single vector shadow register set bit 1 = single vector is presented with a shadow register set 0 = single vector is not present ed with a shadow register set bit 15-13 unimplemented: read as ? 0 ? bit 12 mvec: multi vector configuration bit 1 = interrupt controller confi gured for multi vectored mode 0 = interrupt controller configured for single vectored mode bit 11 unimplemented: read as ? 0 ? bit 10-8 tpc<2:0>: temporal proximity control bits 111 = interrupts of group priority 7 or lower start the tp timer ? ? ? 010 = interrupts of group priority 2 or lower start the tp timer 001 = interrupts of group priority 1 start the ip timer 000 = disables proximity timer bit 7-5 unimplemented: read as ? 0 ? bit 4 int4ep: external interrupt 4 edge polarity control bit 1 = rising edge 0 = falling edge bit 3 int3ep: external interrupt 3 edge polarity control bit 1 = rising edge 0 = falling edge bit 2 int2ep: external interrupt 2 edge polarity control bit 1 = rising edge 0 = falling edge bit 1 int1ep: external interrupt 1 edge polarity control bit 1 = rising edge 0 = falling edge bit 0 int0ep: external interrupt 0 edge polarity control bit 1 = rising edge 0 = falling edge www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 91 pic32mx1xx/2xx register 7-2: intstat: interrupt status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? ripl<2:0> (1) 7:0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? vec<5:0> (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-11 unimplemented: read as ? 0 ? bit 10-8 ripl<2:0>: requested priority level bits (1) 000-111 = the priority level of the late st interrupt presented to the cpu bit 7-6 unimplemented: read as ? 0 ? bit 5-0 vec<5:0>: interrupt vector bits (1) 00000-11111 = the interrupt vector that is presented to the cpu note 1: this value should only be used when the interr upt controller is configured for single vector mode. register 7-3: tptmr: tempor al proximity timer register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 tptmr<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 tptmr<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 tptmr<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 tptmr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 tptmr<31:0>: temporal proximity timer reload bits used by the temporal proximity timer as a reload valu e when the temporal proximity timer is triggered by an interrupt event. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 92 preliminary ? 2011-2012 microchip technology inc. register 7-4: ifsx: interrupt flag status register (1) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ifs31 ifs30 ifs29 ifs28 ifs27 ifs26 ifs25 ifs24 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ifs23 ifs22 ifs21 ifs20 ifs19 ifs18 ifs17 ifs16 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ifs15 ifs14 ifs13 ifs12 ifs11 ifs10 ifs09 ifs08 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ifs07 ifs06 ifs05 ifs04 ifs03 ifs02 ifs01 ifs00 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 ifs31-ifs00: interrupt flag status bits 1 = interrupt request has occurred 0 = no interrupt request has occurred note 1: this register represents a generic defini tion of the ifsx register. refer to ta b l e 7 - 1 for the exact bit definitions. register 7-5: iecx: interrupt enable control register (1) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iec31 iec30 iec29 iec28 iec27 iec26 iec25 iec24 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iec23 iec22 iec21 iec20 iec19 iec18 iec17 iec16 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iec15 iec14 iec13 iec12 iec11 iec10 iec09 iec08 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iec07 iec06 iec05 iec04 iec03 iec02 iec01 iec00 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 iec31-iec00: interrupt enable bits 1 = interrupt is enabled 0 = interrupt is disabled note 1: this register represents a generic definition of the iecx register. refer to ta b l e 7 - 1 for the exact bit definitions. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 93 pic32mx1xx/2xx register 7-6: ipcx: interrupt priority control register (1) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ip03<2:0> is03<1:0> 23:16 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ip02<2:0> is02<1:0> 15:8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ip01<2:0> is01<1:0> 7:0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ip00<2:0> is00<1:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-29 unimplemented: read as ? 0 ? bit 28-26 ip03<2:0>: interrupt priority bits 111 = interrupt priority is 7 ? ? ? 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 25-24 is03<1:0>: interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpiority is 0 bit 23-21 unimplemented: read as ? 0 ? bit 20-18 ip02<2:0>: interrupt priority bits 111 = interrupt priority is 7 ? ? ? 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 17-16 is02<1:0>: interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 15-13 unimplemented: read as ? 0 ? bit 12-10 ip01<2:0>: interrupt priority bits 111 = interrupt priority is 7 ? ? ? 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled note 1: this register represents a generic defini tion of the ipcx register. refer to ta b l e 7 - 1 for the exact bit definitions. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 94 preliminary ? 2011-2012 microchip technology inc. bit 9-8 is01<1:0>: interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 7-5 unimplemented: read as ? 0 ? bit 4-2 ip00<2:0>: interrupt priority bits 111 = interrupt priority is 7 ? ? ? 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 1-0 is00<1:0>: interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 register 7-6: ipcx: interrupt priority control register (1) (continued) note 1: this register represents a generic definition of the ipcx register. refer to ta b l e 7 - 1 for the exact bit definitions. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 95 pic32mx1xx/2xx 8.0 oscillator configuration the pic32mx1xx/2xx oscill ator system has the following modules and features: ? a total of four external and internal oscillator options as clock sources ? on-chip pll with user-selectable input divider, multiplier and output divider to boost operating frequency on select internal and external oscillator sources ? on-chip user-selectable divisor postscaler on select oscillator sources ? software-controllable switching between various clock sources ? a fail-safe clock moni tor (fscm) that detects clock failure and permits safe application recovery or shutdown ? dedicated on-chip pll for usb peripheral a block diagram of the osci llator system is provided in figure 8-1 . note 1: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 6. ?oscillator configuration? (ds61112) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 96 preliminary ? 2011-2012 microchip technology inc. figure 8-1: pic32mx1xx/2x x family clock diagram timer1, rtcc clock control logic fail-safe clock monitor fscm int fscm event cosc<2:0> nosc<2:0> oswen fscmen<1:0> pll secondary oscillator (s osc ) soscen and fsoscen sosco sosci primary oscillator p osc (xt, hs, ec) cpu and select peripherals peripherals frcdiv<2:0> wdt, pwrt 8 mhz typical frc 31.25 khz typical frc oscillator lprc oscillator s osc lprc frcdiv tun<5:0> div 16 postscaler fpllidiv<2:0> pbdiv<1:0> frc/16 postscaler cosc<2:0> f in div x div y pllodiv<2:0> div x 32.768 khz pllmult<2:0> pbclk (t pb ) uf in = 4 mhz pll x24 usb clock (48 mhz) div 2 upllen ufrcen div x upllidiv<2:0> uf in 4 mhz f in 5 mhz c1 (3) c2 (3) xtal r s (1) enable notes: 1. a series resistor, r s , may be required for at strip cut crystals. 2. the internal feedback resistor, r f , is typically in the range of 2 to 10 m . 3. refer to section 6. ?oscillator configuration? (ds61112) in the ? pic32 family reference manual ? for help in determining the best oscillator components. 4. pbclk out is available on the osc2 pin in certain clock modes. 5. usb pll is available on pic32mx2xx devices only. osc2 (4) osc1 r f (2) to internal logic usb pll (5) (p osc ) div 2 to a d c sysclk refclki refclko oe to spi rosel<3:0> p osc frc lprc s osc pbclk sysclk xtpll, hspll, ecpll, frcpll system usb pll n m 512 --------- - + ?? ?? rodiv<4:0> (n) rotrim<8:0> (m) www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 97 pic32mx1xx/2xx register 8-1: osccon: os cillator control register (1) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 r/w-y r/w-y r/w-y r/w-0 r/w-0 r/w-1 ? ? pllodiv<2:0> frcdiv<2:0> 23:16 u-0 r-0 r-1 r/w-y r/w-y r/w-y r/w-y r/w-y ? soscrdy pbdivrdy pbdiv<1:0> pllmult<2:0> 15:8 u-0 r-0 r-0 r-0 u-0 r/w-y r/w-y r/w-y ? cosc<2:0> ? nosc<2:0> 7:0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-y r/w-0 clklock ulock (2) slock slpen cf ufrcen (2) soscen oswen legend: y = value set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-30 unimplemented: read as ? 0 ? bit 29-27 pllodiv<2:0>: output divider for pll 111 = pll output divided by 256 110 = pll output divided by 64 101 = pll output divided by 32 100 = pll output divided by 16 011 = pll output divided by 8 010 = pll output divided by 4 001 = pll output divided by 2 000 = pll output divided by 1 bit 26-24 frcdiv<2:0>: internal fast rc (frc) oscillator clock divider bits 111 = frc divided by 256 110 = frc divided by 64 101 = frc divided by 32 100 = frc divided by 16 011 = frc divided by 8 010 = frc divided by 4 001 = frc divided by 2 (default setting) 000 = frc divided by 1 bit 23 unimplemented: read as ? 0 ? bit 22 soscrdy: secondary oscillator (s osc ) ready indicator bit 1 = indicates that the secondary oscillator is running and is stable 0 = secondary oscillator is still warming up or is turned off bit 21 pbdivrdy: peripheral bus clock (pbclk) divisor ready bit 1 = pbdiv<1:0> bits can be written 0 = pbdiv<1:0> bits cannot be written bit 20-19 pbdiv<1:0>: peripheral bus clock (pbclk) divisor bits 11 = pbclk is sysclk divided by 8 (default) 10 = pbclk is sysclk divided by 4 01 = pbclk is sysclk divided by 2 00 = pbclk is sysclk divided by 1 note 1: writes to this register require an unlock sequence. refer to section 6. ?oscillator? (ds61112) in the ?pic32 family reference manual? for details. 2: this bit is available on pic32mx2xx devices only. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 98 preliminary ? 2011-2012 microchip technology inc. bit 18-16 pllmult<2:0>: phase-locked loop (pll) multiplier bits 111 = clock is multiplied by 24 110 = clock is multiplied by 21 101 = clock is multiplied by 20 100 = clock is multiplied by 19 011 = clock is multiplied by 18 010 = clock is multiplied by 17 001 = clock is multiplied by 16 000 = clock is multiplied by 15 bit 15 unimplemented: read as ? 0 ? bit 14-12 cosc<2:0>: current oscillator selection bits 111 = internal fast rc (frc) oscillat or divided by osccon bits 110 = internal fast rc (frc) oscillator divided by 16 101 = internal low-power rc (lprc) oscillator 100 = secondary oscillator (s osc ) 011 = primary oscillator (p osc ) with pll module (xtpll, hspll or ecpll) 010 = primary oscillator (p osc ) (xt, hs or ec) 001 = internal fast rc oscillator with pll module via postscaler (frcpll) 000 = internal fast rc (frc) oscillator bit 11 unimplemented: read as ? 0 ? bit 10-8 nosc<2:0>: new oscillator selection bits 111 = internal fast rc oscillator (f rc) divided by osccon bits 110 = internal fast rc osc illator (frc) divided by 16 101 = internal low-power rc (lprc) oscillator 100 = secondary oscillator (s osc ) 011 = primary oscillator with pll module (xtpll, hspll or ecpll) 010 = primary oscillator (xt, hs or ec) 001 = internal fast internal rc oscillator with pll module via postscaler (frcpll) 000 = internal fast internal rc oscillator (frc) on reset, these bits are set to the value of the fnosc configuration bits (devcfg1<2:0>). bit 7 clklock: clock selection lock enable bit if clock switching and monitoring is disabled ( fcksm<1:0> = 1x ): 1 = clock and pll selections are locked 0 = clock and pll selections are not locked and may be modified if clock switching and monitoring is enabled (fcksm<1:0> = 0x ): clock and pll selections are never locked and may be modified. bit 6 ulock: usb pll lock status bit (2) 1 = indicates that the usb pll module is in lock or usb pll module start-up timer is satisfied 0 = indicates that the usb pll module is out of lock or usb pll module start-up timer is in progress or usb pll is disabled bit 5 slock: pll lock status bit 1 = pll module is in lock or pll module start-up timer is satisfied 0 = pll module is out of lock, pll start-up timer is running or pll is disabled bit 4 slpen: sleep mode enable bit 1 = device will enter sleep mode when a wait instruction is executed 0 = device will enter idle mode when a wait instruction is executed bit 3 cf: clock fail detect bit 1 = fscm has detected a clock failure 0 = no clock failure has been detected register 8-1: osccon: os cillator control register (1) note 1: writes to this register require an unlock sequence. refer to section 6. ?oscillator? (ds61112) in the ?pic32 family reference manual? for details. 2: this bit is available on pic32mx2xx devices only. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 99 pic32mx1xx/2xx bit 2 ufrcen: usb frc clock enable bit (2) 1 = enable frc as the clock so urce for the usb clock source 0 = use the primary oscillator or usb pll as the usb clock source bit 1 soscen: secondary oscillator (s osc ) enable bit 1 = enable secondary oscillator 0 = disable secondary oscillator bit 0 oswen: oscillator switch enable bit 1 = initiate an oscillator switch to selection specified by nosc<2:0> bits 0 = oscillator switch is complete register 8-1: osccon: os cillator control register (1) note 1: writes to this register require an unlock sequence. refer to section 6. ?oscillator? (ds61112) in the ?pic32 family reference manual? for details. 2: this bit is available on pic32mx2xx devices only. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 100 preliminary ? 2011-2012 microchip technology inc. register 8-2: osctun: frc tuning register (1) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 r-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 r-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? tun<5:0> (2) legend: y = value set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-6 unimplemented: read as ? 0 ? bit 5-0 tun<5:0>: frc oscillator tuning bits (2) 100000 = center frequency -12.5% 100001 = ? ? ? 111111 = 000000 = center frequency. oscillator runs at minimal frequency (8 mhz) 000001 = ? ? ? 011110 = 011111 = center frequency +12.5% note 1: writes to this register require an unlock sequence. refer to section 6. ?oscillator? (ds61112) in the ?pic32 family reference manual? for details. 2: osctun functionality has been provided to help cust omers compensate for temperature effects on the frc frequency over a wide range of temperatures. the tuning step size is an approximation, and is neither characterized, nor tested. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 101 pic32mx1xx/2xx register 8-3: refocon: refere nce oscillator control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? rodiv<14:8> (3) 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rodiv<7:0> (3) 15:8 r/w-0 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0, hc r-0, hs, hc on ?sidloe rslp (2) ? divswen active 7:0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? rosel<3:0> (1) legend: hc = hardware clearable hs = hardware settable r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 unimplemented: read as ? 0 ? bit 30-16 rodiv<14:0> reference clock divider bits (1) 111111111111111 = output clock is source clock frequency divided by 65,534 111111111111110 = output clock is source clock frequency divided by 65,532 ? ? ? 000000000000010 = output clock is source clock frequency divided by 4 000000000000001 = output clock is source clock frequency divided by 2 000000000000000 = output clock is same frequency as source clock (no divider) bit 15 on: output enable bit 1 = reference oscillator module enabled 0 = reference oscillator module disabled bit 14 unimplemented: read as ? 0 ? bit 13 sidl: peripheral stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12 oe: reference clock output enable bit 1 = reference clock is driven out on refclko pin 0 = reference clock is not driven out on refclko pin bit 11 rslp: reference oscillator module run in sleep bit (2) 1 = reference oscillator module output continues to run in sleep 0 = reference oscillator module output is disabled in sleep bit 10 unimplemented: read as ? 0 ? bit 9 divswen: divider switch enable bit 1 = divider switch is in progress 0 = divider switch is complete bit 8 active: reference clock request status bit 1 = reference clock request is active 0 = reference clock request is not active note 1: the rosel and rodiv bits should not be written while the active bit is ? 1 ?, as undefined behavior may result. 2: this bit is ignored when the rosel<3:0> bits = 0000 or 0001 . 3: while the on bit is set to ? 1 ?, writes to these bits do not take effe ct until the divswen bit is also set to? 1 ?. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 102 preliminary ? 2011-2012 microchip technology inc. bit 7-4 unimplemented: read as ? 0 ? bit 3-0 rosel<3:0>: reference clock source select bits (1) 1111 = reserved; do not use ? ? ? 1001 = reserved; do not use 1000 = refclki 0111 = system pll output 0110 = usb pll output 0101 =s osc 0100 =lprc 0011 =frc 0010 =p osc 0001 = pbclk 0000 = sysclk register 8-3: refocon: reference oscillator control register note 1: the rosel and rodiv bits should not be written while the active bit is ? 1 ?, as undefined behavior may result. 2: this bit is ignored when the rosel<3:0> bits = 0000 or 0001 . 3: while the on bit is set to ? 1 ?, writes to these bits do not take effe ct until the divswen bit is also set to? 1 ?. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 103 pic32mx1xx/2xx register 8-4: refotrim: refere nce oscillator trim register (1,2) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rotrim<8:1> 23:16 r/w-0 r-0 u-0 u-0 u-0 u-0 u-0 u-0 rotrim<0> ? ? ? ? ? ? ? 15:8 u-0 r-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? legend: y = value set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-23 rotrim<8:0>: reference oscillator trim bits 111111111 = 511/512 divisor added to rodiv value 111111110 = 510/512 divisor added to rodiv value ? ? ? 100000000 = 256/512 divisor added to rodiv value ? ? ? 000000010 = 2/512 divisor added to rodiv value 000000001 = 1/512 divisor added to rodiv value 000000000 = 0/512 divisor added to rodiv value bit 22-0 unimplemented: read as ? 0 ? note 1: while the on bit (refocon<15>) is ? 1 ?, writes to this register do not take effect until the divswen bit is also set to ? 1 ?. 2: this register is not available on all devices. refer to the specific device data sheet for availability. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 104 preliminary ? 2011-2012 microchip technology inc. notes: www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 105 pic32mx1xx/2xx 9.0 direct memory access (dma) controller the pic32 direct memory acce ss (dma) controller is a bus master module useful for data transfers between different devices without cpu intervention. the source and destination of a dma transfer can be any of the memory mapped modules exis tent in the pic32 (such as peripheral bus (pbus) devices: spi, uart, pmp, etc.) or memory itself. following are some of the key features of the dma controller module: ? four identical channels, each featuring: - auto-increment source and destination address registers - source and destination pointers - memory to memory and memory to peripheral transfers ? automatic word-size detection: - transfer granularity, down to byte level - bytes need not be word-aligned at source and destination ? fixed priority channel arbitration ? flexible dma channel operating modes: - manual (software) or automatic (interrupt) dma requests - one-shot or auto-repe at block transfer modes - channel-to-channel chaining ? flexible dma requests: - a dma request can be selected from any of the peripheral interrupt sources - each channel can select any (appropriate) observable interrupt as its dma request source - a dma transfer abort can be selected from any of the peripheral interrupt sources - pattern (data) match transfer termination ? multiple dma channel status interrupts: - dma channel block transfer complete - source empty or half empty - destination full or half full - dma transfer aborted due to an external event - invalid dma address generated ? dma debug support features: - most recent address accessed by a dma channel - most recent dma channel to transfer data ? crc generation module: - crc module can be assigned to any of the available channels - crc module is highly configurable figure 9-1: dma block diagram note 1: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 31. ?direct memory access (dma) controller? (ds61117) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. address decoder channel 0 control channel 1 control channel n control global control (dmacon) bus interface channel priority arbitration s e l s e l y i 0 i 1 i 2 i n system irq int controller device bus + bus arbitration peripheral bus www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 106 preliminary ? 2011-2012 microchip technology inc. register 9-1: dmacon: dma co ntroller control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 u-0 r/w-0 r/w-0 u-0 u-0 u-0 on (1) ? ? suspend dmabusy ? ? ? 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: dma on bit (1) 1 = dma module is enabled 0 = dma module is disabled bit 14-13 unimplemented: read as ? 0 ? bit 12 suspend: dma suspend bit 1 = dma transfers are suspended to allow cpu uninterrupted access to data bus 0 = dma operates normally bit 11 dmabusy: dma module busy bit (4) 1 = dma module is active 0 = dma module is disabled and not actively transferring data bit 10-0 unimplemented: read as ? 0 ? note 1: when using 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 107 pic32mx1xx/2xx register 9-2: dmastat: dma status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 r-0 r-0 r-0 r-0 ? ? ? ? rdwr dmach<2:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-4 unimplemented: read as ? 0 ? bit 3 rdwr: read/write status bit 1 = last dma bus access was a read 0 = last dma bus access was a write bit 2-0 dmach<2:0>: dma channel bits these bits contain the value of the most recent active dma channel. register 9-3: dmaaddr: dma address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dmaaddr<31:24> 23:16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dmaaddr<23:16> 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dmaaddr<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dmaaddr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 dmaaddr<31:0>: dma module address bits these bits contain the address of the most recent dma access. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 108 preliminary ? 2011-2012 microchip technology inc. register 9-4: dcrccon: dm a crc control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 ? ?byto<1:0>wbo (1) ? ?bito 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? plen<4:0> 7:0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 crcen crcapp (1) crctyp ? ? crcch<2:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-30 unimplemented: read as ? 0 ? bit 29-28 byto<1:0>: crc byte order selection bits 11 = endian byte swap on half-word boundaries (i.e., sour ce half-word order with reverse source byte order per half-word) 10 = swap half-words on word boundaries (i.e., revers e source half-word order with source byte order per half-word) 01 = endian byte swap on word boundaries (i.e., reverse source byte order) 00 = no swapping (i.e., source byte order) bit 27 wbo: crc write byte order selection bit (1) 1 = source data is written to the destina tion re-ordered as defined by byto<1:0> 0 = source data is written to the destination unaltered bit 26-25 unimplemented: read as ? 0 ? bit 24 bito: crc bit order selection bit (4) when crctyp (dcrccon<15>) = 1 (crc module is in ip header mode): 1 = the ip header checksum is calculated least significant bit (lsb) first (i.e., reflected) 0 = the ip header checksum is calculated most significant bit (msb) first (i.e., not reflected) when crctyp (dcrccon<15>) = 0 (crc module is in lfsr mode): 1 = the lfsr crc is calculated least significant bit first (i.e., reflected) 0 = the lfsr crc is calculated most sign ificant bit first (i.e., not reflected) bit 23-13 unimplemented: read as ? 0 ? bit 12-8 plen<4:0>: polynomial length bits (1) when crctyp (dcrccon<15>) = 1 (crc module is in ip header mode): these bits are unused. when crctyp (dcrccon<15>) = 0 (crc module is in lfsr mode): denotes the length of the polynomial ? 1. bit 7 crcen: crc enable bit 1 = crc module is enabled and channel transfers are routed through the crc module 0 = crc module is disabled and channel transfers proceed normally note 1: when wbo = 1 , unaligned transfers are not support ed and the crcapp bit cannot be set. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 109 pic32mx1xx/2xx bit 6 crcapp: crc append mode bit (1) 1 = the dma transfers data from the source into the crc but not to the destination. when a block transfer completes the dma writes the calculated crc value to the location given by chxdsa 0 = the dma transfers data from the source through the crc obeying wbo as it writes the data to the destination bit 5 crctyp: crc type selection bit 1 = the crc module will calculate an ip header checksum 0 = the crc module will calculate a lfsr crc bit 4-3 unimplemented: read as ? 0 ? bit 2-0 crcch<2:0>: crc channel select bits 111 = crc is assigned to channel 7 110 = crc is assigned to channel 6 101 = crc is assigned to channel 5 100 = crc is assigned to channel 4 011 = crc is assigned to channel 3 010 = crc is assigned to channel 2 001 = crc is assigned to channel 1 000 = crc is assigned to channel 0 register 9-4: dcrccon: dma crc co ntrol register (continued) note 1: when wbo = 1 , unaligned transfers are not support ed and the crcapp bit cannot be set. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 110 preliminary ? 2011-2012 microchip technology inc. register 9-5: dcrcdata: dma crc data register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcdata<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcdata<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcdata<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcdata<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 dcrcdata<31:0>: crc data register bits writing to this register will seed t he crc generator. reading from this regi ster will return the current value of the crc. bits greater than plen will return ? 0 ? on any read. when crctyp (dcrccon<15>) = 1 (crc module is in ip header mode): only the lower 16 bits contain ip header checksum information. the upper 16 bits are always ? 0 ?. data written to this register is conver ted and read back in 1?s complement form (i.e., current ip header checksum value). when crctyp (dcrccon<15>) = 0 (crc module is in lfsr mode): bits greater than plen will return ? 0 ? on any read. register 9-6: dcrcxor: dma crcxor enable register (1,2,3) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcxor<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcxor<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcxor<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcxor<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 dcrcxor<31:0>: crc xor register bits when crctyp (dcrccon<15>) = 1 (crc module is in ip header mode): this register is unused. when crctyp (dcrccon<15>) = 0 (crc module is in lfsr mode): 1 = enable the xor input to the shift register 0 = disable the xor input to the shift register; data is shifted in directly from the previous stage in the register www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 111 pic32mx1xx/2xx register 9-7: dchxcon: dma channel x control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 chbusy ? ? ? ? ? ? chchns (1) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r-0 r/w-0 r/w-0 chen (2) chaed chchn chaen ? chedet chpri<1:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 chbusy: channel busy bit 1 = channel is active or has been enabled 0 = channel is inactive or has been disabled bit 14-9 unimplemented: read as ? 0 ? bit 8 chchns: chain channel selection bit (1) 1 = chain to channel lower in natural priority (ch1 will be enabled by ch2 transfer complete) 0 = chain to channel higher in natural priority (ch1 will be enabled by ch0 transfer complete) bit 7 chen: channel enable bit (2) 1 = channel is enabled 0 = channel is disabled bit 6 chaed: channel allow events if disabled bit 1 = channel start/abort events will be regi stered, even if the channel is disabled 0 = channel start/abort events will be ignored if the channel is disabled bit chchn: channel chain enable bit 1 = allow channel to be chained 0 = do not allow channel to be chained bit 4 chaen: channel automatic enable bit 1 = channel is continuously enabled, and not automat ically disabled after a block transfer is complete 0 = channel is disabled on block transfer complete bit 3 unimplemented: read as ? 0 ? bit 2 chedet: channel event detected bit 1 = an event has been detected 0 = no events have been detected bit 1-0 chpri<1:0>: channel priority bits 11 = channel has priority 3 (highest) 10 = channel has priority 2 01 = channel has priority 1 00 = channel has priority 0 note 1: the chain selection bit takes effect when chaining is enabled (i.e., chchn = 1 ). 2: when the channel is suspended by clearing this bit, the user application should poll the chbusy bit (if available on the device variant) to see when the channel is suspended, as it may take some clock cycles to complete a current transacti on before the channel is suspended. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 112 preliminary ? 2011-2012 microchip technology inc. register 9-8: dchxecon: dma channel x event control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 chairq<7:0> (1) 15:8 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 chsirq<7:0> (1) 7:0 s-0 s-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 cforce cabort paten sirqen airqen ? ? ? legend: s = settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-24 unimplemented: read as ? 0 ? bit 23-16 chairq<7:0>: channel transfer abort irq bits (1) 11111111 = interrupt 255 will abort any transfers in progress and set chaif flag ? ? ? 00000001 = interrupt 1 will abort any transfers in progress and set chaif flag 00000000 = interrupt 0 will abort any transfers in progress and set chaif flag bit 15-8 chsirq<7:0>: channel transfer start irq bits (1) 11111111 = interrupt 255 will initiate a dma transfer ? ? ? 00000001 = interrupt 1 will initiate a dma transfer 00000000 = interrupt 0 will initiate a dma transfer bit 7 cforce: dma forced transfer bit 1 = a dma transfer is forced to begin when this bit is written to a ? 1 ? 0 = this bit always reads ? 0 ? bit 6 cabort: dma abort transfer bit 1 = a dma transfer is aborted when this bit is written to a ? 1 ? 0 = this bit always reads ? 0 ? bit 5 paten: channel pattern match abort enable bit 1 = abort transfer and clear chen on pattern match 0 = pattern match is disabled bit 4 sirqen: channel start irq enable bit 1 = start channel cell transfer if an interrupt matching chsirq occurs 0 = interrupt number chsirq is ignor ed and does not start a transfer bit 3 airqen: channel abort irq enable bit 1 = channel transfer is aborted if an interrupt matching chairq occurs 0 = interrupt number chairq is ignor ed and does not terminate a transfer bit 2-0 unimplemented: read as ? 0 ? note 1: see table 7-1: ?interrupt irq, vector and bit location? for the list of available interrupt irq sources. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 113 pic32mx1xx/2xx register 9-9: dchxint: dma channel x interrupt control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chsdie chshie chddie chdhie chb cie chccie chtaie cherie 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chsdif chshif chddif chdhif chbcif chccif chtaif cherif legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-24 unimplemented: read as ? 0 ? bit 23 chsdie: channel source done interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 22 chshie: channel source half empty interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 21 chddie: channel destination done interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 20 chdhie: channel destination half full interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 19 chbcie: channel block transfer complete interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 18 chccie: channel cell transfer complete interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 17 chtaie: channel transfer abort interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 16 cherie: channel address error interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 15-8 unimplemented: read as ? 0 ? bit 7 chsdif: channel source done interrupt flag bit 1 = channel source pointer has reached end of source (chsptr = chssiz) 0 = no interrupt is pending bit 6 chshif: channel source half empty interrupt flag bit 1 = channel source pointer has reached mi dpoint of source (chsptr = chssiz/2) 0 = no interrupt is pending bit 5 chddif: channel destination done interrupt flag bit 1 = channel destination pointer has reached end of destination (chdptr = chdsiz) 0 = no interrupt is pending www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 114 preliminary ? 2011-2012 microchip technology inc. bit 4 chdhif: channel destination half full interrupt flag bit 1 = channel destination pointer has reached midpoint of destination (chdptr = chdsiz/2) 0 = no interrupt is pending bit 3 chbcif: channel block transfer complete interrupt flag bit 1 = a block transfer has been completed (the larger of chssiz/chdsiz bytes has been transferred), or a pattern match event occurs 0 = no interrupt is pending bit 2 chccif: channel cell transfer complete interrupt flag bit 1 = a cell transfer has been completed (chcsiz bytes have been transferred) 0 = no interrupt is pending bit 1 chtaif: channel transfer abort interrupt flag bit 1 = an interrupt matching chairq has been det ected and the dma transfer has been aborted 0 = no interrupt is pending bit 0 cherif: channel address error interrupt flag bit 1 = a channel address error has been detected either the source or the destination address is invalid. 0 = no interrupt is pending register 9-9: dchxint: dma channel x interrupt control register (continued) www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 115 pic32mx1xx/2xx register 9-10: dchxssa: dma chann el x source start address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chssa<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chssa<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chssa<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chssa<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 chssa<31:0> channel source start address bits channel source start address. note: this must be the physical address of the source. register 9-11: dchxdsa: dma channel x destination start address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chdsa<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chdsa<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chdsa<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chdsa<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 chdsa<31:0>: channel destination start address bits channel destination start address. note: this must be the physical address of the destination. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 116 preliminary ? 2011-2012 microchip technology inc. register 9-12: dchxssiz: dma channel x source size register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chssiz<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chssiz<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 chssiz<15:0>: channel source size bits 1111111111111111 = 65,535 byte source size ? ? ? 0000000000000010 = 2 byte source size 0000000000000001 = 1 byte source size 0000000000000000 = 65,536 byte source size register 9-13: dchxdsiz: dma chann el x destination size register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chdsiz<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chdsiz<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 chdsiz<15:0>: channel destination size bits 1111111111111111 = 65,535 byte destination size ? ? ? 0000000000000010 = 2 byte destination size 0000000000000001 = 1 byte destination size 0000000000000000 = 65,536 byte destination size www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 117 pic32mx1xx/2xx register 9-14: dchxsptr: dma channel x source pointer register (1) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chsptr<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chsptr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 chsptr<15:0>: channel source pointer bits 1111111111111111 = points to byte 65,535 of the source ? ? ? 0000000000000001 = points to byte 1 of the source 0000000000000000 = points to byte 0 of the source note 1: when in pattern detect mode, this regi ster is reset on a pattern detect. register 9-15: dchxdptr: dma channe l x destination pointer register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chdptr<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chdptr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 chdptr<15:0>: channel destination pointer bits 1111111111111111 = points to byte 65,535 of the destination ? ? ? 0000000000000001 = points to byte 1 of the destination 0000000000000000 = points to byte 0 of the destination www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 118 preliminary ? 2011-2012 microchip technology inc. register 9-16: dchxcsiz: dma channel x cell-size register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chcsiz<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chcsiz<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 chcsiz<15:0>: channel cell-size bits 1111111111111111 = 65,535 bytes transferred on an event ? ? ? 0000000000000010 = 2 bytes transferred on an event 0000000000000001 = 1 byte transferred on an event 0000000000000000 = 65,536 bytes transferred on an event register 9-17: dchxcptr: dma channel x cell pointer register (1) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chcptr<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chcptr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 chcptr<7:0>: channel cell progress pointer bits 1111111111111111 = 65,535 bytes have been tran sferred since the last event ? ? ? 0000000000000001 = 1 byte has been transferred since the last event 0000000000000000 = 0 bytes have been transferred since the last event note 1: when in pattern detect mode, this register is reset on a pattern detect. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 119 pic32mx1xx/2xx register 9-18: dchxdat: dma channel x pattern data register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chpdat<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7-0 chpdat<7:0>: channel data register bits pattern terminate mode: data to be matched must be stored in this register to allow terminate on match. all other modes: unused. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 120 preliminary ? 2011-2012 microchip technology inc. notes: www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 121 pic32mx1xx/2xx 10.0 usb on-the-go (otg) the universal serial bus (usb) module contains analog and digital components to provide a usb 2.0 full-speed and low-speed embedded host, full-speed device or otg implementation with a minimum of external components. this module in host mode is intended for use as an embedded host and therefore does not implement a uhci or ohci controller. the usb module consists of the clock generator, the usb voltage comparators, the transceiver, the serial interface engine (sie), a dedicated usb dma control- ler, pull-up and pull-down resistors, and the register interface. a block diagram of the pic32 usb otg module is presented in figure 10-1 . the clock generator provides the 48 mhz clock required for usb full-speed and low-speed communi- cation. the voltage comparators monitor the voltage on the v bus pin to determine the state of the bus. the transceiver provides t he analog translation between the usb bus and the digital logic. the sie is a state machine that transfers data to and from the endpoint buffers and generates the hardware protocol for data transfers. the usb dma controller transfers data between the data buffers in ram and the sie. the inte- grated pull-up and pull-down resistors eliminate the need for external signaling components. the register interface allows the cpu to configure and communicate with the module. the pic32 usb module includes the following features: ? usb full-speed support for host and device ? low-speed host support ? usb otg support ? integrated signaling resistors ? integrated analog comparators for v bus monitoring ? integrated usb transceiver ? transaction handshaking performed by hardware ? endpoint buffering anywhere in system ram ? integrated dma to acce ss system ram and flash note 1: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 27. ?usb on- the-go (otg)? (ds61126) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: the implementation and use of the usb specifications, as well as other third party specifications or technologies, may require licensing; including, but not limited to, usb implementers forum, inc. (also referred to as usb-if). the user is fully responsible for investigating and satisfying any applicable licensing obligations. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 122 preliminary ? 2011-2012 microchip technology inc. figure 10-1: pic32mx1xx/2xx family usb interface diagram osc1 osc2 primary oscillator 8mhztypical frc oscillator tun<5:0> (3) pll 48 mhz usb clock (6) div x upllen (5) ufrcen (2) (p osc ) upllidiv (5) uf in (4) div 2 v usb 3 v 3 d+ (1) d- (1) id (7) bus transceiver sie v buson (7) comparators usb srp charge srp discharge registers and control interface transceiver power 3.3v usb module voltage system ram full speed pull-up host pull-down low speed pull-up host pull-down id pull-up dma note 1: pins can be used as digital inputs when usb is not enabled. 2: this bit field is contai ned in the osccon register. 3: this bit field is contained in the osctrm register. 4: usb pll u f in requirements: 4 mhz. 5: this bit field is contained in the devcfg2 register. 6: a 48 mhz clock is required for proper usb operation. 7: pins can be used as gpio wh en the usb module is disabled. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 123 pic32mx1xx/2xx register 10-1: u1otgir: usb otg interrupt status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs u-0 r/wc-0, hs idif t1msecif lstateif actvif sesvdif sesendif ? vbusvdif legend: wc = write ?1? to clear hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 idif: id state change indicator bit 1 = change in id state detected 0 = no change in id state detected bit 6 t1msecif: 1 millisecond timer bit 1 = 1 millisecond timer has expired 0 = 1 millisecond timer has not expired bit 5 lstateif: line state stable indicator bit 1 = usb line state has been stable for 1 ms, but different from last time 0 = usb line state has not been stable for 1 ms bit 4 actvif: bus activity indicator bit 1 = activity on the d+, d-, id or v bus pins has caused the device to wake-up 0 = activity has not been detected bit 3 sesvdif: session valid change indicator bit 1 =v bus voltage has dropped below the session end level 0 =v bus voltage has not dropped below the session end level bit 2 sesendif: b-device v bus change indicator bit 1 = a change on the session end input was detected 0 = no change on the session end input was detected bit 1 unimplemented: read as ? 0 ? bit 0 vbusvdif: a-device v bus change indicator bit 1 = change on the session valid input detected 0 = no change on the session valid input detected www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 124 preliminary ? 2011-2012 microchip technology inc. register 10-2: u1otgie: usb otg interrupt enable register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 idie t1msecie lstateie actvie sesvdie sesendie ? vbusvdie legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 idie: id interrupt enable bit 1 = id interrupt enabled 0 = id interrupt disabled bit 6 t1msecie: 1 millisecond timer interrupt enable bit 1 = 1 millisecond timer interrupt enabled 0 = 1 millisecond timer interrupt disabled bit 5 lstateie: line state interrupt enable bit 1 = line state interrupt enabled 0 = line state interrupt disabled bit 4 actvie: bus activity interrupt enable bit 1 = activity interrupt enabled 0 = activity interrupt disabled bit 3 sesvdie: session valid interrupt enable bit 1 = session valid interrupt enabled 0 = session valid interrupt disabled bit 2 sesendie: b-session end interrupt enable bit 1 = b-session end interrupt enabled 0 = b-session end interrupt disabled bit 1 unimplemented: read as ? 0 ? bit 0 vbusvdie: a-v bus valid interrupt enable bit 1 =a-v bus valid interrupt enabled 0 =a-v bus valid interrupt disabled www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 125 pic32mx1xx/2xx register 10-3: u1otgstat: usb otg status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r-0 u-0 r-0 u-0 r-0 r-0 u-0 r-0 id ?lstate ? sesvd sesend ? vbusvd legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 id: id pin state indicator bit 1 = no cable is attached or a type b cable has been plugged into the usb receptacle 0 = a ?type a? otg cable has been plugged into the usb receptacle bit 6 unimplemented: read as ? 0 ? bit 5 lstate: line state stable indicator bit 1 = usb line state (u1con and u1con) has been stable for the previous 1 ms 0 = usb line state (u1con and u1con) has not been stable for the previous 1 ms bit 4 unimplemented: read as ? 0 ? bit 3 sesvd: session valid indicator bit 1 =v bus voltage is above session valid on the a or b device 0 =v bus voltage is below session valid on the a or b device bit 2 sesend: b-session end indicator bit 1 =v bus voltage is below session valid on the b device 0 =v bus voltage is above session valid on the b device bit 1 unimplemented: read as ? 0 ? bit 0 vbusvd: a-v bus valid indicator bit 1 =v bus voltage is above session valid on the a device 0 =v bus voltage is below session valid on the a device www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 126 preliminary ? 2011-2012 microchip technology inc. register 10-4: u1otgcon: usb otg control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dppulup dmpulup dppuldwn dmpuldwn vbuson otgen vbuschg vbusdis legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 dppulup: d+ pull-up enable bit 1 = d+ data line pull-up resistor is enabled 0 = d+ data line pull-up resistor is disabled bit 6 dmpulup: d- pull-up enable bit 1 = d- data line pull-up resistor is enabled 0 = d- data line pull-up resistor is disabled bit 5 dppuldwn: d+ pull-down enable bit 1 = d+ data line pull-down resistor is enabled 0 = d+ data line pull-down resistor is disabled bit 4 dmpuldwn: d- pull-down enable bit 1 = d- data line pull-down resistor is enabled 0 = d- data line pull-down resistor is disabled bit 3 vbuson: v bus power-on bit 1 =v bus line is powered 0 =v bus line is not powered bit 2 otgen: otg functionality enable bit 1 = dppulup, dmpulup, dppuldwn and dmpuldwn bits are under software control 0 = dppulup, dmpulup, dppuldwn and dmpuldwn bits are under usb hardware control bit 1 vbuschg: v bus charge enable bit 1 =v bus line is charged through a pull-up resistor 0 =v bus line is not charged through a resistor bit 0 vbusdis: v bus discharge enable bit 1 =v bus line is discharged through a pull-down resistor 0 =v bus line is not discharged through a resistor www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 127 pic32mx1xx/2xx register 10-5: u1pwrc: usb power control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r-0 u-0 u-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 uactpnd ? ? uslpgrd usbbusy ? ususpend usbpwr legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 uactpnd: usb activity pending bit 1 = usb bus activity has been detected; but an interrupt is pending, it has not been generated yet 0 = an interrupt is not pending bit 6-5 unimplemented: read as ? 0 ? bit 4 uslpgrd: usb sleep entry guard bit 1 = sleep entry is blocked if usb bus activity is detected or if a notification is pending 0 = usb module does not block sleep entry bit 3 usbbusy: usb module busy bit (1) 1 = usb module is active or disabled, but not ready to be enabled 0 = usb module is not active and is ready to be enabled note: when usbpwr = 0 and usbbusy = 1 , status from all other registers is invalid and writes to all usb module registers produce undefined results. bit 2 unimplemented: read as ? 0 ? bit 1 ususpend: usb suspend mode bit 1 = usb module is placed in suspend mode (the 48 mhz usb clock will be gated off. the tr ansceiver is placed in a low-power state.) 0 = usb module operates normally bit 0 usbpwr: usb operation enable bit 1 = usb module is turned on 0 = usb module is disabled (outputs held inactive, device pins not used by usb, analog features are shut down to reduce power consumption.) www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 128 preliminary ? 2011-2012 microchip technology inc. register 10-6: u1ir: usb interrupt register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r-0 r/wc-0, hs stallif attachif (1) resumeif (2) idleif trnif (3) sofif uerrif (4) urstif (5) detachif (6) legend: wc = write ?1? to clear hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 stallif: stall handshake interrupt bit 1 = in host mode a stall handshake was receiv ed during the handshake ph ase of the transaction in device mode a stall handshake was transmitte d during the handshake phase of the transaction 0 = stall handshake has not been sent bit 6 attachif: peripheral attach interrupt bit (1) 1 = peripheral attachment wa s detected by the usb module 0 = peripheral attachment was not detected bit 5 resumeif: resume interrupt bit (2) 1 = k-state is observed on the d+ or d- pin for 2.5 s 0 = k-state is not observed bit 4 idleif: idle detect interrupt bit 1 = idle condition detected (constant idle state of 3 ms or more) 0 = no idle condition detected bit 3 trnif: token processing complete interrupt bit (3) 1 = processing of current token is complete; a read of the u1stat register will provide endpoint information 0 = processing of current token not complete bit 2 sofif: sof token interrupt bit 1 = sof token received by the peripheral or the sof threshold reached by the host 0 = sof token was not received nor threshold reached bit 1 uerrif: usb error condition interrupt bit (4) 1 = unmasked error condition has occurred 0 = unmasked error cond ition has not occurred note 1: this bit is valid only if the hosten bit is set (see register 10-11 ), there is no activity on the usb for 2.5 s, and the current bus state is not se0. 2: when not in suspend mode, this interrupt should be disabled. 3: clearing this bit will cause the stat fifo to advance. 4: only error conditions enabled through the u1eie register will set this bit. 5: device mode. 6: host mode. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 129 pic32mx1xx/2xx bit 0 urstif: usb reset interrupt bit (device mode) (5) 1 = valid usb reset has occurred 0 = no usb reset has occurred detachif: usb detach interrupt bit (host mode) (6) 1 = peripheral detachment was detected by the usb module 0 = peripheral detachment was not detected register 10-6: u1ir: usb interrupt register (continued) note 1: this bit is valid only if the hosten bit is set (see register 10-11 ), there is no activity on the usb for 2.5 s, and the current bus state is not se0. 2: when not in suspend mode, this interrupt should be disabled. 3: clearing this bit will cause the stat fifo to advance. 4: only error conditions enabled through the u1eie register will set this bit. 5: device mode. 6: host mode. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 130 preliminary ? 2011-2012 microchip technology inc. register 10-7: u1ie: usb interrupt enable register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stallie attachie resumeie idleie trnie sofie uerrie (1) urstie (2) detachie (3) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 stallie: stall handshake interrupt enable bit 1 = stall interrupt enabled 0 = stall interrupt disabled bit 6 attachie: attach interrupt enable bit 1 = attach interrupt enabled 0 = attach interrupt disabled bit 5 resumeie: resume interrupt enable bit 1 = resume interrupt enabled 0 = resume interrupt disabled bit 4 idleie: idle detect interrupt enable bit 1 = idle interrupt enabled 0 = idle interrupt disabled bit 3 trnie: token processing complete interrupt enable bit 1 = trnif interrupt enabled 0 = trnif interrupt disabled bit 2 sofie: sof token interrupt enable bit 1 = sofif interrupt enabled 0 = sofif interrupt disabled bit 1 uerrie: usb error interrupt enable bit (1) 1 = usb error interrupt enabled 0 = usb error interrupt disabled bit 0 urstie: usb reset interrupt enable bit (2) 1 = urstif interrupt enabled 0 = urstif interrupt disabled detachie: usb detach interrupt enable bit (3) 1 = dattchif interrupt enabled 0 = dattchif interrupt disabled note 1: for an interrupt to propagate usbif, the uerrie bit (u1ie<1>) must be set. 2: device mode. 3: host mode. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 131 pic32mx1xx/2xx register 10-8: u1eir: usb error interrupt status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs btsef bmxef dmaef (1) btoef (2) dfn8ef crc16ef crc5ef (3,4) pidef eofef (5) legend: wc = write ?1? to clear hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 btsef: bit stuff error flag bit 1 = packet rejected due to bit stuff error 0 = packet accepted bit 6 bmxef: bus matrix error flag bit 1 = the base address, of the bdt, or the address of an individual buffer pointed to by a bdt entry, is invalid. 0 = no address error bit 5 dmaef: dma error flag bit (1) 1 = usb dma error condition detected 0 =no dma error bit 4 btoef: bus turnaround time-out error flag bit (2) 1 = bus turnaround time-out has occurred 0 = no bus turnaround time-out bit 3 dfn8ef: data field size error flag bit 1 = data field received is not an integral number of bytes 0 = data field received is an integral number of bytes bit 2 crc16ef: crc16 failure flag bit 1 = data packet rejected due to crc16 error 0 = data packet accepted note 1: this type of error occurs when the module?s request fo r the dma bus is not granted in time to service the module?s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer size is not sufficient to store the receiv ed data packet causing it to be truncated. 2: this type of error occurs when more than 16-bit-tim es of idle from the previous end-of-packet (eop) has elapsed. 3: this type of error occurs when the module is tran smitting or receiving data and the sof counter has reached zero. 4: device mode. 5: host mode. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 132 preliminary ? 2011-2012 microchip technology inc. bit 1 crc5ef: crc5 host error flag bit (3,4) 1 = token packet rejected due to crc5 error 0 = token packet accepted eofef: eof error flag bit (5) 1 = eof error condition detected 0 = no eof error condition bit 0 pidef: pid check failure flag bit 1 = pid check failed 0 = pid check passed register 10-8: u1eir: usb error interrupt status register (continued) note 1: this type of error occurs when the module?s request fo r the dma bus is not granted in time to service the module?s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer size is not sufficient to store the receiv ed data packet causing it to be truncated. 2: this type of error occurs when more than 16-bit-tim es of idle from the previous end-of-packet (eop) has elapsed. 3: this type of error occurs when the module is tran smitting or receiving data and the sof counter has reached zero. 4: device mode. 5: host mode. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 133 pic32mx1xx/2xx register 10-9: u1eie: usb error interrupt enable register (1) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 btsee bmxee dmaee btoee dfn8ee crc16ee crc5ee (2) pidee eofee (3) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 btsee: bit stuff error interrupt enable bit 1 = btsef interrupt enabled 0 = btsef interrupt disabled bit 6 bmxee: bus matrix error interrupt enable bit 1 = bmxef interrupt enabled 0 = bmxef interrupt disabled bit 5 dmaee: dma error interrupt enable bit 1 = dmaef interrupt enabled 0 = dmaef interrupt disabled bit 4 btoee: bus turnaround time-out error interrupt enable bit 1 = btoef interrupt enabled 0 = btoef interrupt disabled bit 3 dfn8ee: data field size erro r interrupt enable bit 1 = dfn8ef interrupt enabled 0 = dfn8ef interrupt disabled bit 2 crc16ee: crc16 failure interrupt enable bit 1 = crc16ef interrupt enabled 0 = crc16ef interrupt disabled bit 1 crc5ee: crc5 host error interrupt enable bit (2) 1 = crc5ef interrupt enabled 0 = crc5ef interrupt disabled eofee: eof error interrupt enable bit (3) 1 = eof interrupt enabled 0 = eof interrupt disabled bit 0 pidee: pid check failure interrupt enable bit 1 = pidef interrupt enabled 0 = pidef interrupt disabled note 1: for an interrupt to propagate usbif, the uerrie bit (u1ie<1>) must be set. 2: device mode. 3: host mode. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 134 preliminary ? 2011-2012 microchip technology inc. register 10-10: u1stat: usb status register (1) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0u-0u-0u-0u-0u-0u-0u-0 ? ? ? ? ? ? ? ? 23:16 u-0u-0u-0u-0u-0u-0u-0u-0 ? ? ? ? ? ? ? ? 15:8 u-0u-0u-0u-0u-0u-0u-0u-0 ? ? ? ? ? ? ? ? 7:0 r-x r-x r-x r-x r-x r-x u-0 u-0 endpt<3:0> dir ppbi ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7-4 endpt<3:0>: encoded number of last endpoint activity bits (represents the number of the bdt, updated by the last usb transfer.) 1111 = endpoint 15 1110 = endpoint 14 ? ? ? 0001 =endpoint 1 0000 =endpoint 0 bit 3 dir: last bd direction indicator bit 1 = last transaction was a transmit transfer (tx) 0 = last transaction was a receive transfer (rx) bit 2 ppbi: ping-pong bd pointer indicator bit 1 = the last transaction was to the odd bd bank 0 = the last transaction was to the even bd bank bit 1-0 unimplemented: read as ? 0 ? note 1: the u1stat register is a window into a 4-byte fifo maintained by the usb module. u1stat value is only valid when u1ir is active. clearing the u1ir bit advances the fifo. data in register is invalid when u1ir = 0 . www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 135 pic32mx1xx/2xx register 10-11: u1con: usb control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 jstate se0 pktdis (4) usbrst hosten (2) resume (3) ppbrst usben (4) tokbusy (1,5) sofen (5) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 jstate: live differential receiver jstate flag bit 1 = jstate detected on the usb 0 = no jstate detected bit 6 se0: live single-ended zero flag bit 1 = single ended zero detected on the usb 0 = no single ended zero detected bit 5 pktdis: packet transfer disable bit (4) 1 = token and packet processing disabled (set upon setup token received) 0 = token and packet processing enabled tokbusy: token busy indicator bit (1,5) 1 = token being executed by the usb module 0 = no token being executed bit 4 usbrst: module reset bit (5) 1 = usb reset generated 0 = usb reset terminated bit 3 hosten: host mode enable bit (2) 1 = usb host capability enabled 0 = usb host capability disabled bit 2 resume: resume signaling enable bit (3) 1 = resume signaling activated 0 = resume signaling disabled note 1: software is required to check this bit before issu ing another token command to the u1tok register (see register 10-15 ). 2: all host control logic is reset any time that the value of this bit is toggled. 3: software must set resume for 10 ms if the part is a function, or for 25 ms if the part is a host, and then clear it to enable remote wake-up. in host mode , the usb module will append a low-speed eop to the resume signaling when this bit is cleared. 4: device mode. 5: host mode. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 136 preliminary ? 2011-2012 microchip technology inc. bit 1 ppbrst: ping-pong buffers reset bit 1 = reset all even/odd buffer pointers to the even bd banks 0 = even/odd buffer pointers not being reset bit 0 usben: usb module enable bit (4) 1 = usb module and supporting circuitry enabled 0 = usb module and supporting circuitry disabled sofen: sof enable bit (5) 1 = sof token sent every 1 ms 0 = sof token disabled register 10-11: u1con: usb control register (continued) note 1: software is required to check this bit before issu ing another token command to the u1tok register (see register 10-15 ). 2: all host control logic is reset any time that the value of this bit is toggled. 3: software must set resume for 10 ms if the part is a function, or for 25 ms if the part is a host, and then clear it to enable remote wake-up. in host mode , the usb module will append a low-speed eop to the resume signaling when this bit is cleared. 4: device mode. 5: host mode. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 137 pic32mx1xx/2xx register 10-12: u1addr: usb address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 lspden devaddr<6:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 lspden: low speed enable indicator bit 1 = next token command to be executed at low speed 0 = next token command to be executed at full speed bit 6-0 devaddr<6:0>: 7-bit usb device address bits register 10-13: u1frml: usb frame number low register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 frml<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7-0 frml<7:0>: the 11-bit frame number lower bits the register bits are updated with the current fr ame number whenever a sof token is received. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 138 preliminary ? 2011-2012 microchip technology inc. register 10-14: u1frmh: usb frame number high register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 u-0 r-0 r-0 r-0 ? ? ? ? ? frmh<2:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-3 unimplemented: read as ? 0 ? bit 2-0 frmh<2:0>: the upper 3 bits of the frame numbers bits the register bits are updated with the current fr ame number whenever a sof token is received. register 10-15: u1tok: usb token register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pid<3:0> (1) ep<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7-4 pid<3:0>: token type indicator bits (1) 0001 = out (tx) token type transaction 1001 = in (rx) token type transaction 1101 = setup (tx) token type transaction note: all other values are rese rved and must not be used. bit 3-0 ep<3:0>: token command endpoint address bits the four bit value must specify a valid endpoint. note 1: all other values are rese rved and must not be used. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 139 pic32mx1xx/2xx register 10-16: u1sof: usb sof threshold register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cnt<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7-0 cnt<7:0>: sof threshold value bits typical values of the threshold are: 01001010 = 64-byte packet 00101010 = 32-byte packet 00011010 = 16-byte packet 00010010 = 8-byte packet register 10-17: u1bdtp1: usb bdt page 1 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 bdtptrl<15:9> ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7-1 bdtptrl<15:9>: bdt base address bits this 7-bit value provides address bits 15 through 9 of the bdt base address, which defines the starting location of the bdt in system memory. the 32-bit bdt base address is 512-byte aligned. bit 0 unimplemented: read as ? 0 ? www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 140 preliminary ? 2011-2012 microchip technology inc. register 10-18: u1bdtp2: usb bdt page 2 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bdtptrh<23:16> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7-0 bdtptrh<23:16>: bdt base address bits this 8-bit value provides address bits 23 through 16 of the bdt base address, which defines the starting location of the bdt in system memory. the 32-bit bdt base address is 512-byte aligned. register 10-19: u1bdtp3: usb bdt page 3 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bdtptru<31:24> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7-0 bdtptru<31:24>: bdt base address bits this 8-bit value provides address bits 31 through 24 of the bdt base address, defines the starting location of the bdt in system memory. the 32-bit bdt base address is 512-byte aligned. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 141 pic32mx1xx/2xx register 10-20: u1cnfg1: us b configuration 1 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 u-0 r/w-0 u-0 u-0 u-0 r/w-0 uteye uoemon ? usbsidl ? ? ? uasuspnd legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 uteye: usb eye-pattern test enable bit 1 = eye-pattern test enabled 0 = eye-pattern test disabled bit 6 uoemon: usb oe monitor enable bit 1 = oe signal active; it indicates intervals during which the d+/d- lines are driving 0 = oe signal inactive bit 5 unimplemented: read as ? 0 ? bit 4 usbsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 3-1 unimplemented: read as ? 0 ? bit 0 uasuspnd: automatic suspend enable bit 1 = usb module automatically suspends upon entry to sleep mode. see the ususpend bit (u1pwrc<1>) in register 10-5 . 0 = usb module does not automatically suspend upon entry to sleep mode. software must use the ususpend bit (u1pwrc<1>) to suspend the module, including the usb 48 mhz clock www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 142 preliminary ? 2011-2012 microchip technology inc. register 10-21: u1ep0-u1ep15: usb endpoint control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 lspd retrydis ? epcondis eprxen eptxen epstall ephshk legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 lspd: low-speed direct connection enable bit (host mode and u1ep0 only) 1 = direct connection to a low-speed device enabled 0 = direct connection to a low-speed device disabled; hub required with pre_pid bit 6 retrydis: retry disable bit (host mode and u1ep0 only) 1 = retry nak?d transactions disabled 0 = retry nak?d transactions enabled; retry done in hardware bit 5 unimplemented: read as ? 0 ? bit 4 epcondis: bidirectional endpoint control bit if eptxen = 1 and eprxen = 1 : 1 = disable endpoint n from control transfers; only tx and rx transfers allowed 0 = enable endpoint n for control (setup) transfers; tx and rx transfers also allowed otherwise, this bit is ignored. bit 3 eprxen: endpoint receive enable bit 1 = endpoint n receive enabled 0 = endpoint n receive disabled bit 2 eptxen: endpoint transmit enable bit 1 = endpoint n transmit enabled 0 = endpoint n transmit disabled bit 1 epstall: endpoint stall status bit 1 = endpoint n was stalled 0 = endpoint n was not stalled bit 0 ephshk: endpoint handshake enable bit 1 = endpoint handshake enabled 0 = endpoint handshake disabled (typically used for isochronous endpoints) www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 143 pic32mx1xx/2xx 11.0 i/o ports general purpose i/o pins ar e the simplest of peripher- als. they allow the pic ? mcu to monitor and control other devices. to add flexib ility and functionality, some pins are multiplexed with alternate function(s). these functions depend on which peripheral features are on the device. in general, when a peripheral is functioning, that pin may not be used as a general purpose i/o pin. following are some of the key features of this module: ? individual output pin open-drain enable/disable ? individual input pin weak pull-up and pull-down ? monitor selective inputs and generate interrupt when change in pin state is detected ? operation during cpu sleep and idle modes ? fast bit manipulation using clr, set and inv registers figure 11-1 illustrates a block diagram of a typical multiplexed i/o port. figure 11-1: block diagram of a typical multiplexed port structure note 1: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 12. ?i/o ports? (ds61120) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. peripheral output data peripheral module peripheral output enable pio module peripheral module enable wr lat i/o pin wr port data bus rd lat rd port rd tris wr tris 0 1 rd odc sysclk q d ck en q q d ck en q q d ck en q q d ck q q d ck q 0 1 sysclk wr odc odc tris lat sleep 1 0 1 0 output multiplexers i/o cell synchronization r peripheral input legend: r = peripheral input buffer types may vary. refer to ta b l e 1 - 1 for peripheral details. note: this block diagram is a general representation of a shared port/ peripheral structure for illustration purposes only. the actual structure for any specific port/peripheral combination may be different than it is shown here. peripheral input buffer www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 144 preliminary ? 2011-2012 microchip technology inc. 11.1 parallel i/o (pio) ports all port pins have ten regi sters directly associated with their operation as digital i/o. the data direction register (trisx) determines whether t he pin is an input or an output. if the data direction bit is a ? 1 ?, then the pin is an input. all port pins are defined as inputs after a reset. reads from the latch (latx) read the latch. writes to the latch write the latch. reads from the port (portx) read the port pins, while writes to the port pins write the latch. 11.1.1 open-drain configuration in addition to the portx, latx, and trisx registers for data control, some port pins can also be individually configured for either digital or open-drain output. this is controlled by the open-drain control register, odcx, associated with each port. setting any of the bits con- figures the corresponding pin to act as an open-drain output. the open-drain feature allo ws the generation of out- puts higher than v dd (e.g., 5v) on any desired 5v-tol- erant pins by using external pull-up resistors. the maximum open-drain voltage allowed is the same as the maximum v ih specification. see the ?pin diagrams? section for the available pins and their functionality. 11.1.2 configuring analog and digital port pins the anselx register controls the operation of the analog port pins. the port pins that are to function as analog inputs must have their corresponding ansel and tris bits set. in order to use port pins for i/o functionality with digital modules, such as timers, uarts, etc., the corresponding anselx bit must be cleared. the anselx register has a default value of 0xffff; therefore, all pins that share analog functions are analog (not digital) by default. if the tris bit is cleared (output) while the anselx bit is set, the digital output level (v oh or v ol ) is converted by an analog peripheral, such as the adc module or comparator module. when the port register is read, all pins configured as analog input channels are read as cleared (a low level). pins configured as digital inputs do not convert an analog input. analog levels on any pin defined as a digital input (including the anx pins) can cause the input buffer to consume current that exceeds the device specifications. 11.1.3 i/o port write/read timing one instruction cycle is required between a port direction change or port write operation and a read operation of the same port. typically this instruction would be an nop . 11.1.4 input change notification the input change notification function of the i/o ports allows the pic32mx1xx/2xx devices to generate interrupt requests to the processor in response to a change-of-state on selected input pins. this feature can detect input change-of-sta tes even in sleep mode, when the clocks are disabled . every i/o port pin can be selected (enabled) for generating an interrupt request on a change-of-state. five control registers are associated with the cn func- tionality of each i/o port. the cnenx registers contain the cn interrupt enable control bits for each of the input pins. setting any of these bits enables a cn interrupt for the corresponding pins. the cnstatx register indicates whether a change occurred on the corresponding pin since the last read of the portx bit. each i/o pin also has a weak pull-up and a weak pull-down connected to it. the pull-ups act as a current source or sink source connected to the pin, and eliminate the need for external resistors when push-button or keypad de vices are connected. the pull-ups and pull-downs are enabled separately using the cnpux and the cnpdx registers, which contain the control bits for each of the pins. setting any of the control bits enables the weak pull-ups and/or pull-downs for the corresponding pins. an additional control regi ster (cnconx) is shown in register 11-3 . 11.2 clr, set and inv registers every i/o module register has a corresponding clr (clear), set (set) and inv (invert) register designed to provide fast atomic bit manipulations. as the name of the register implies, a va lue written to a set, clr or inv register effectively performs the implied operation, but only on the corresponding base register and only bits specified as ? 1 ? are modified. bits specified as ? 0 ? are not modified. reading set, clr and inv registers returns undefined values. to see the affects of a write operation to a set, clr or inv register, the base register must be read. note: pull-ups and pull-downs on change notifi- cation pins should always be disabled when the port pin is configured as a digital output. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 145 pic32mx1xx/2xx 11.3 peripheral pin select a major challenge in general purpose devices is provid- ing the largest possible set of peripheral features while minimizing the conflict of features on i/o pins. the chal- lenge is even greater on low pin-count devices. in an application where more than one peripheral needs to be assigned to a single pin, inconvenient workarounds in application code or a complete redesign may be the only option. peripheral pin select configuration provides an alternative to these choices by enabling peripheral set selection and their placement on a wide range of i/o pins. by increasing the pinout options available on a particular device, users can better tailor the device to their entire application, rather than trimming the application to fit the device. the peripheral pin select configuration feature oper- ates over a fixed subset of digital i/o pins. users may independently map the input an d/or output of most dig- ital peripherals to these i/o pins. peripheral pin select is performed in software and generally does not require the device to be reprogrammed. hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping once it has been established. 11.3.1 available pins the number of available pins is dependent on the particular device and its pin co unt. pins that support the peripheral pin select feat ure include the designation ?rpn? in their full pin designation, where ?rp? designates a remappable peripheral and ?n? is the remappable port number. 11.3.2 available peripherals the peripherals managed by the peripheral pin select are all digital-only peripherals. these include general serial communications (uart and spi), general pur- pose timer clock inputs, time r-related peripherals (input capture and output compare) and interrupt-on-change inputs. in comparison, some digital-only peripheral modules are never included in the peri pheral pin select feature. this is because the peripheral?s function requires spe- cial i/o circuitry on a specific port and cannot be easily connected to multiple pins. these modules include i 2 c among others. a similar requirement excludes all mod- ules with analog inputs, such as the analog-to-digital converter (adc). a key difference between remappable and non-remap- pable peripherals is that remappable peripherals are not associated with a default i/o pin. the peripheral must always be assigned to a specific i/o pin before it can be used. in contrast, non-remappable peripherals are always available on a defau lt pin, assuming that the peripheral is active and not conflicting with another peripheral. when a remappable peripheral is active on a given i/o pin, it takes priority over all other digital i/o and digital communication peripherals associated with the pin. priority is given regardless of the type of peripheral that is mapped. remappable peripherals never take priority over any analog functions associated with the pin. 11.3.3 controlling peripheral pin select peripheral pin select features are controlled through two sets of sfrs: one to map peripheral inputs, and one to map outputs. because they are separately con- trolled, a particular peripher al?s input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. the association of a peripheral to a peripheral-select- able pin is handled in two different ways, depending on whether an input or output is being mapped. 11.3.4 input mapping the inputs of the peripheral pin select options are mapped on the basis of the peripheral. that is, a control register associated with a peripheral dictates the pin it will be mapped to. the [ pin name ] r registers, where [ pin name ] refers to the periph eral pins listed in table 11-1 , are used to configure peripheral input mapping (see register 11-1 ). each register contains sets of 4 bit fields. programming these bit fields with an appropriate value maps the rpn pin with the corresponding value to that peripheral. for any given device, the valid range of values for any bit field is shown in table 11-1 . for example, figure 11-2 illustrates the remappable pin selection for the u1rx input. figure 11-2: remappable input example for u1rx rpa2 rpb6 rpa4 0 1 2 u1rx input u1rxr<3:0> to peripheral rpn n note: for input only, peripheral pin select functionality does not have priority over trisx settings. therefore, when configuring rpn pin for input, the corresponding bit in the trisx register must also be configured for input (set to ? 1 ?). www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 146 preliminary ? 2011-2012 microchip technology inc. table 11-1: input pin selection peripheral pin [ pin name ]r sfr [ pin name ]r bits [ pin name ]r value to rpn pin selection int4 int4r int4r<3:0> 0000 = rpa0 0001 = rpb3 0010 = rpb4 0011 = rpb15 0100 = rpb7 0101 = rpc7 0110 = rpc0 0111 = rpc5 1000 = reserved ? ? ? 1111 = reserved t2ck t2ckr t2ckr<3:0> ic4 ic4r ic4r<3:0> ss1 ss1r ss1r<3:0> refclki refclkir refclkir<3:0> int3 int3r int3r<3:0> 0000 = rpa1 0001 = rpb5 0010 = rpb1 0011 = rpb11 0100 = rpb8 0101 = rpa8 0110 = rpc8 0111 = rpa9 1000 = reserved ? ? ? 1111 = reserved t3ck t3ckr t3ckr<3:0> ic3 ic3r ic3r<3:0> u1cts u1ctsr u1ctsr<3:0> u2rx u2rxr u2rxr<3:0> sdi1 sdi1r sdi1r<3:0> int2 int2r int2r<3:0> 0000 = rpa2 0001 = rpb6 0010 = rpa4 0011 = rpb13 0100 = rpb2 0101 = rpc6 0110 = rpc1 0111 = rpc3 1000 = reserved ? ? ? 1111 = reserved t4ck t4ckr t4ckr<3:0> ic1 ic1r ic1r<3:0> ic5 ic5r ic5r<3:0> u1rx u1rxr u1rxr<3:0> u2cts u2ctsr u2ctsr<3:0> sdi2 sdi2r sdi2r<3:0> ocfb ocfbr ocfbr<3:0> int1 int1r int1r<3:0> 0000 = rpa3 0001 = rpb14 0010 = rpb0 0011 = rpb10 0100 = rpb9 0101 = rpc9 0110 = rpc2 0111 = rpc4 1000 = reserved ? ? ? 1111 = reserved t5ck t5ckr t5ckr<3:0> ic2 ic2r ic2r<3:0> ss2 ss2r ss2r<3:0> ocfa ocfar ocfar<3:0> www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 147 pic32mx1xx/2xx 11.3.5 output mapping in contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. in this case, a control regi ster associated with a particular pin dictates the peripheral output to be mapped. the rpnr registers ( register 11-2 ) are used to control output mapping. like the [ pin name ]r registers, each register cont ains sets of 4 bit fields. the value of the bit field corresponds to one of the peripherals, and that peripheral?s output is mapped to the pin (see table 11-2 and figure 11-3 ). a null output is associated wit h the output register reset value of ? 0 ?. this is done to ensure that remappable outputs remain disconnect ed from all output pins by default. figure 11-3: example of multiplexing of remappable output for rpa0 11.3.6 controlling configuration changes because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. pic32 devices include two features to prevent alterations to the peripheral map: ? control register lock sequence ? configuration bit select lock 11.3.6.1 control register lock under normal operation, writes to the rpnr and [ pin name ]r registers are not allowed. attempted writes appear to execute normally, but the contents of the registers remain unchanged. to change these regis- ters, they must be unlocked in hardware. the regis- ter lock is controlled by th e iolock configuration bit (cfgcon<13>). setting iolock prevents writes to the control registers; clear ing iolock allows writes. to set or clear the iolock bit, an unlock sequence must be executed. refer to section 6. ?oscillator? (ds61112) in the ?pic32 family reference manual? for details. 11.3.6.2 configuration bit select lock as an additional level of safety, the device can be configured to prevent more than one write session to the rpnr and [ pin name ]r registers. the iol1way configuration bit (devcfg3<29>) blocks the iolock bit from being cleared after it has been set once. if iolock remains set, the register unlock procedure does not execute, and the pe ripheral pin select control registers cannot be written to. the only way to clear the bit and re-enable peripheral remapping is to perform a device reset. in the default (unprogramm ed) state, iol1way is set, restricting users to one write session. rpa0r<3:0> 0 15 1 default u1tx output u1rts output 2 14 output data rpa0 www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 148 preliminary ? 2011-2012 microchip technology inc. table 11-2: output pin selection rpn port pin rpnr sfr rpnr bits rpnr value to peripheral selection rpa0 rpa0r rpa0r<3:0> 0000 = no connect 0001 = u1tx 0010 = u2rts 0011 = ss1 0100 = reserved 0101 = oc1 0110 = reserved 0111 = c2out 1000 = reserved ? ? ? 1111 = reserved rpb3 rpb3r rpb3r<3:0> rpb4 rpb4r rpb4r<3:0> rpb15 rpb15r rpb15r<3:0> rpb7 rpb7r rpb7r<3:0> rpc7 rpc7r rpc7r<3:0> rpc0 rpc0r rpc0r<3:0> rpc5 rpc5r rpc5r<3:0> rpa1 rpa1r rpa1r<3:0> 0000 = no connect 0001 = reserved 0010 = reserved 0011 = sdo1 0100 = sdo2 0101 = oc2 0110 = reserved ? ? ? 1111 = reserved rpb5 rpb5r rpb5r<3:0> rpb1 rpb1r rpb1r<3:0> rpb11 rpb11r rpb11r<3:0> rpb8 rpb8r rpb8r<3:0> rpa8 rpa8r rpa8r<3:0> rpc8 rpc8r rpc8r<3:0> rpa9 rpa9r rpa9r<3:0> rpa2 rpa2r rpa2r<3:0> 0000 = no connect 0001 = reserved 0010 = reserved 0011 = sdo1 0100 = sdo2 0101 = oc4 0110 = oc5 0111 = refclko 1000 = reserved ? ? ? 1111 = reserved rpb6 rpb6r rpb6r<3:0> rpa4 rpa4r rpa4r<3:0> rpb13 rpb13r rpb13r<3:0> rpb2 rpb2r rpb2r<3:0> rpc6 rpc6r rpc6r<3:0> rpc1 rpc1r rpc1r<3:0> rpc3 rpc3r rpc3r<3:0> rpa3 rpa3r rpa3r<3:0> 0000 = no connect 0001 = u1rts 0010 = u2tx 0011 = reserved 0100 = ss2 0101 = oc3 0110 = reserved 0111 = c1out 1000 = reserved ? ? ? 1111 = reserved rpb14 rpb14r rpb14r<3:0> rpb0 rpb0r rpb0r<3:0> rpb10 rpb10r rpb10r<3:0> rpb9 rpb9r rpb9r<3:0> rpc9 rpc9r rpc9r<3:0> rpc2 rpc2r rpc2r<3:0> rpc4 rpc4r rpc4r<3:0> www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 149 pic32mx1xx/2xx register 11-1: [ pin name ]r: peripheral pin sel ect input register (1) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ?[ pin name ]r<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-4 unimplemented: read as ? 0 ? bit 3-0 [ pin name ]r<3:0>: peripheral pin select input bits where [ pin name ] refers to the pins that are used to configure peripheral input mapping. see table 11-1 for input pin selection values. note 1: register values can only be changed if t he iolock configuration bit (cfgcon<13>) = 0 . register 11-2: rpnr: periphera l pin select output register (1) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ?rpnr<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-4 unimplemented: read as ? 0 ? bit 3-0 rpnr<3:0>: peripheral pin select output bits see ta b l e 11 - 2 for output pin selection values. note 1: register values can only be changed if t he iolock configuration bit (cfgcon<13>) = 0 . www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 150 preliminary ? 2011-2012 microchip technology inc. register 11-3: cnconx: change notice cont rol for portx register (x = a, b, c) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 on ?sidl ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: change notice (cn) control on bit 1 = cn is enabled 0 = cn is disabled bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle control bit 1 = cpu idle mode halts cn operation 0 = cpu idle does not affect cn operation bit 12-0 unimplemented: read as ? 0 ? www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 151 pic32mx1xx/2xx 12.0 timer1 this family of pic32 devices features one synchronous/asynchronous 16-bit timer that can operate as a free-running interval timer for various timing applica- tions and counting external events. this timer can also be used with the low-power secondary oscillator (s osc ) for real-time clock (rtc) applications. the following modes are supported: ? synchronous internal timer ? synchronous internal gated timer ? synchronous external timer ? asynchronous external timer 12.1 additional supported features ? selectable clock prescaler ? timer operation during cpu idle and sleep mode ? fast bit manipulation using clr, set and inv registers ? asynchronous mode can be used with the s osc to function as a real-time clock (rtc) figure 12-1: timer1 block diagram (1) note 1: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 14. ?timers? (ds61105) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. on sync sosci sosco/t1ck pr1 t1if equal 16-bit comparator tmr1 reset soscen event flag 1 0 tsync tgate tgate pbclk 1 0 tcs gate sync tckps<1:0> prescaler 2 1, 8, 64, 256 x 1 1 0 0 0 q qd note 1: the default state of the soscen bit (osccon<1> ) during a device reset is controlled by the fsoscen bit in configuration word, devcfg1. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 152 preliminary ? 2011-2012 microchip technology inc. register 12-1: t1con: type a timer control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 r/w-0 r-0 u-0 u-0 u-0 on (1) ? sidl twdis twip ? ? ? 7:0 r/w-0 u-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 u-0 tgate ? tckps<1:0> ? tsync tcs ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: timer on bit (1) 1 = timer is enabled 0 = timer is disabled bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit 1 = discontinue operation when device enters idle mode 0 = continue operation even in idle mode bit 12 twdis: asynchronous timer write disable bit 1 = writes to tmr1 are ignored until pending write operation completes 0 = back-to-back writes are enabled (legacy asynchronous timer functionality) bit 11 twip: asynchronous timer write in progress bit in asynchronous timer mode: 1 = asynchronous write to tmr1 register in progress 0 = asynchronous write to tmr1 register complete in synchronous timer mode: this bit is read as ? 0 ?. bit 10-8 unimplemented: read as ? 0 ? bit 7 tgate: timer gated time accumulation enable bit when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 6 unimplemented: read as ? 0 ? bit 5-4 tckps<1:0>: timer input clock pr escale select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value note 1: when using 1:1 pbcmlk divisor, the user?s software should not read/write the peripheral sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 153 pic32mx1xx/2xx bit 3 unimplemented: read as ? 0 ? bit 2 tsync: timer external clock input synchronization selection bit when tcs = 1 : 1 = external clock input is synchronized 0 = external clock input is not synchronized when tcs = 0 : this bit is ignored. bit 1 tcs: timer clock source select bit 1 = external clock from txcki pin 0 = internal peripheral clock bit 0 unimplemented: read as ? 0 ? register 12-1: t1con: type a time r control register (continued) note 1: when using 1:1 pbcmlk divisor, the user?s software should not read/write the peripheral sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 154 preliminary ? 2011-2012 microchip technology inc. notes: www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 155 pic32mx1xx/2xx 13.0 timer2/3, timer4/5 this family of pic32 devices features four synchronous 16-bit timers (default) that can operate as a free- running interval timer for various timing applications and counting external events. the following modes are supported: ? synchronous internal 16-bit timer ? synchronous internal 16-bit gated timer ? synchronous external 16-bit timer two 32-bit synchronous timers are available by combining timer2 with timer3 and timer4 with timer5. the 32-bit timers can operate in three modes: ? synchronous internal 32-bit timer ? synchronous internal 32-bit gated timer ? synchronous external 32-bit timer 13.1 additional supported features ? selectable clock prescaler ? timers operational during cpu idle ? time base for input capture and output compare modules (timer2 and timer3 only) ? adc event trigger (timer3 only) ? fast bit manipulation using clr, set and inv registers figure 13-1: timer2, 3, 4, 5 block diagram (16-bit) note 1: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 14. ?timers? (ds61105) of the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: in this chapter, references to registers, txcon, tmrx and prx, use ?x? to repre- sent timer2 through 5 in 16-bit modes. in 32-bit modes, ?x? represents timer2 or 4; ?y? represents timer3 or 5. sync prx txif equal comparator x 16 tmrx reset event flag q q d tgate 1 0 gate txck sync on tgate tcs tckps prescaler 3 1, 2, 4, 8, 16, 32, 64, 256 x 1 1 0 0 0 pbclk trigger (1) adc event note 1: adc event trigger is available on timer3 only. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 156 preliminary ? 2011-2012 microchip technology inc. figure 13-2: timer2/3, 4/5 block diagram (32-bit) (1) tmry tmrx tyif event equal 32-bit comparator pry prx reset ls half word ms half word flag note 1: in this diagram, the use of ?x? in registers, txcon, tmrx, prx and txck, refers to either timer2 or timer4; the use of ?y? in registers, tycon, tmry, pry, tyif, refers to either timer3 or timer5. 2: adc event trigger is available only on the timer2/3 pair. tgate 0 1 pbclk gate txck sync sync adc event trigger (2) on tgate tcs tckps prescaler 3 1, 2, 4, 8, 16, 32, 64, 256 1 0 0 0 q q d x 1 www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 157 pic32mx1xx/2xx register 13-1: txcon: type b timer control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 on (1,3) ?sidl (4) ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 tgate (3) tckps<2:0> (3) t32 (2) ?tcs (3) ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: timer on bit (1,3) 1 = module is enabled 0 = module is disabled bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit (4) 1 = discontinue operation when device enters idle mode 0 = continue operation even in idle mode bit 12-8 unimplemented: read as ? 0 ? bit 7 tgate: timer gated time accumulation enable bit (3) when tcs = 1 : this bit is ignored and is read as ? 0 ?. when tcs = 0 : 1 = gated time accumu lation is enabled 0 = gated time accumu lation is disabled bit 6-4 tckps<2:0>: timer input clock prescale select bits (3) 111 = 1:256 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value note 1: when using 1:1 pbclk divisor, the user?s software should not read/write the peripheral sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 2: this bit is available only on even numbered timers (timer2 and timer4). 3: while operating in 32-bit mode, this bit has no effect for odd numbered timers (timer1, timer3, and timer5). all timer functions are se t through the even numbered timers. 4: while operating in 32-bit mode, this bit must be clea red on odd numbered timers to enable the 32-bit timer in idle mode. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 158 preliminary ? 2011-2012 microchip technology inc. bit 3 t32: 32-bit timer mode select bit (2) 1 = odd numbered and even numbered timers form a 32-bit timer 0 = odd numbered and even numbered timers form a separate 16-bit timer bit 2 unimplemented: read as ? 0 ? bit 1 tcs: timer clock source select bit (3) 1 = external clock from txck pin 0 = internal peripheral clock bit 0 unimplemented: read as ? 0 ? register 13-1: txcon: type b timer control register (continued) note 1: when using 1:1 pbclk divisor, the user?s software should not read/write the peripheral sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 2: this bit is available only on even numbered timers (timer2 and timer4). 3: while operating in 32-bit mode, this bit has no effect for odd numbered timers (timer1, timer3, and timer5). all timer functions are se t through the even numbered timers. 4: while operating in 32-bit mode, this bit must be cl eared on odd numbered timers to enable the 32-bit timer in idle mode. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 159 pic32mx1xx/2xx 14.0 input capture the input capture module is useful in applications requiring frequency (period) and pulse measurement. the input capture module capt ures the 16-bit or 32-bit value of the selected time base registers when an event occurs at the icx pin. the following events cause capture events: 1. simple capture event modes - capture timer value on every falling edge of input at icx pin - capture timer value on every rising edge of input at icx pin 2. capture timer value on every edge (rising and falling) 3. capture timer value on every edge (rising and falling), specified edge first. 4. prescaler capture event modes - capture timer value on every 4th rising edge of input at icx pin - capture timer value on every 16th rising edge of input at icx pin each input capture channel can select between one of two 16-bit timers (timer2 or timer3) for the time base, or two 16-bit timers (timer2 and timer3) together to form a 32-bit timer. the se lected timer can use either an internal or external clock. other operational features include: ? device wake-up from capture pin during cpu sleep and idle modes ? interrupt on input capture event ? 4-word fifo buffer for capture values interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled ? input capture can also be used to provide additional sources of external interrupts figure 14-1: input capture block diagram note 1: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 15. ?input capture? (ds61122) of the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: an ?x? in a signal, register or bit name denotes the number of the capture channel. fifo control icxbuf tmr2 tmr3 capture event /n fifo ici<1:0> icm<2:0> icm<2:0> 101 100 011 010 001 001 111 to cpu set flag icxif (in ifsx register) rising edge mode prescaler mode (4th rising edge) falling edge mode edge detection prescaler mode (16th rising edge) sleep/idle wake-up mode c32/ictmr icx pin mode 110 specified/every edge mode fedge www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 160 preliminary ? 2011-2012 microchip technology inc. register 14-1: ic x con: input capture x control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 on (1) ?sidl ? ? ?fedgec32 7:0 r/w-0 r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 ictmr ici<1:0> icov icbne icm<2:0> legend: r = readable bit w = writable bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = un known) p = programmable bit r = reserved bit bit 31-16 unimplemented: read as ? 0 ? bit 15 on: input capture module enable bit (1) 1 = module enabled 0 = disable and reset module, disable clocks, disable interrupt generation and allow sfr modifications bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle control bit 1 = halt in cpu idle mode 0 = continue to operate in cpu idle mode bit 12-10 unimplemented: read as ? 0 ? bit 9 fedge: first capture edge select bit (only used in mode 6, icm<2:0> = 110 ) 1 = capture rising edge first 0 = capture falling edge first bit 8 c32: 32-bit capture select bit 1 = 32-bit timer resource capture 0 = 16-bit timer resource capture bit 7 ictmr: timer select bit (does not affect timer selection when c32 (icxcon<8>) is ? 1 ?) 0 = timer3 is the counter source for capture 1 = timer2 is the counter source for capture bit 6-5 ici<1:0>: interrupt control bits 11 = interrupt on every fourth capture event 10 = interrupt on every third capture event 01 = interrupt on every second capture event 00 = interrupt on every capture event bit 4 icov: input capture overflow status flag bit (read-only) 1 = input capture overflow occurred 0 = no input capture overflow occurred bit 3 icbne: input capture buffer not empty status bit (read-only) 1 = input capture buffer is not empty; at least one more capture value can be read 0 = input capture buffer is empty note 1: when using 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 161 pic32mx1xx/2xx bit 2-0 icm<2:0>: input capture mode select bits 111 = interrupt-only mode (only supported while in sleep mode or idle mode) 110 = simple capture event mode ? every edge, sp ecified edge first and every edge thereafter 101 = prescaled capture event mode ? every sixteenth rising edge 100 = prescaled capture event mode ? every fourth rising edge 011 = simple capture event mode ? every rising edge 010 = simple capture event mode ? every falling edge 001 = edge detect mode ? every edge (rising and falling) 000 = input capture module is disabled register 14-1: ic x con: input capture x control register (continued) note 1: when using 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 162 preliminary ? 2011-2012 microchip technology inc. notes: www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 163 pic32mx1xx/2xx 15.0 output compare the output compare module (ocmp) is used to gen- erate a single pulse or a tr ain of pulses in response to selected time base events. for all modes of operation, the ocmp module compares the values stored in the ocxr and/or the ocxrs registers to the value in the selected timer. when a match occurs, the ocmp module generates an event based on the selected mode of operation. the following are some of the key features: ? multiple output compare modules in a device ? programmable interrupt generation on compare event ? single and dual compare modes ? single and continuous output pulse generation ? pulse-width modulation (pwm) mode ? hardware-based pwm fault detection and automatic output disable ? programmable selection of 16-bit or 32-bit time bases ? can operate from either of two available 16-bit time bases or a single 32-bit time base figure 15-1: output compare module block diagram note 1: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 16. ?output compare? (ds61111) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. ocxr (1) comparator output logic q s r ocm<2:0> output enable ocx (1) set flag bit ocxif (1) ocxrs (1) mode select 3 note 1: where ?x? is shown, reference is made to the register s associated with the respec tive output compare channels, 1 through 5. 2: the ocfa pin controls the oc1-oc4 channels. the ocfb pin controls the oc5 channel. 0 1 octsel 0 1 16 16 ocfa or ocfb (2) timer2 timer2 timer3 logic output enable timer3 rollover rollover www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 164 preliminary ? 2011-2012 microchip technology inc. register 15-1: ocxcon: output compare ?x? control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 on (1) ?sidl ? ? ? ? ? 7:0 u-0 u-0 r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? oc32 ocflt (2) octsel ocm<2:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: output compare peripheral on bit (1) 1 = output compare peripheral is enabled 0 = output compare peripheral is disabled bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit 1 = discontinue operation when cpu enters idle mode 0 = continue operation in idle mode bit 12-6 unimplemented: read as ? 0 ? bit 5 oc32: 32-bit compare mode bit 1 = ocxr<31:0> and/or ocxrs<31:0> are used fo r comparisions to the 32-bit timer source 0 = ocxr<15:0> and ocxrs<15:0> are used for comparisons to the 16-bit timer source bit 4 ocflt: pwm fault condition status bit (2) 1 = pwm fault condition has occurred (cleared in hw only) 0 = no pwm fault condition has occurred bit 3 octsel: output compare timer select bit 1 = timer3 is the clock s ource for this ocmp module 0 = timer2 is the clock s ource for this ocmp module bit 2-0 ocm<2:0>: output compare mode select bits 111 = pwm mode on ocx; fault pin enabled 110 = pwm mode on ocx; fault pin disabled 101 = initialize ocx pin low; generate continuous output pulses on ocx pin 100 = initialize ocx pin low; generate single output pulse on ocx pin 011 = compare event toggles ocx pin 010 = initialize ocx pin high; compare event forces ocx pin low 001 = initialize ocx pin low; compare event forces ocx pin high 000 = output compare peripheral is dis abled but continues to draw current note 1: when using 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 2: this bit is only used when ocm<2:0> = ? 111 ?. it is read as ? 0 ? in all other modes. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 165 pic32mx1xx/2xx 16.0 serial peripheral interface (spi) the spi module is a synchronous serial interface that is useful for communicatin g with external peripherals and other microcontroller devices. these peripheral devices may be serial eeprom s, shift registers, dis- play drivers, analog-to-digit al converters (adc), etc. the pic32 spi module is compatible with motorola ? spi and siop interfaces. some of the key features of the spi module are: ? master and slave modes support ? four different clock formats ? enhanced framed spi protocol support ? user-configurable 8-bit, 16-bit and 32-bit data width ? separate spi fifo buffers for receive and transmit - fifo buffers act as 4/8/16-level deep fifos based on 32/16/8-bit data width ? programmable interrupt event on every 8-bit, 16-bit and 32-bit data transfer ? operation during cpu sleep and idle mode ? audio codec support: -i 2 s protocol - left-justified - right-justified -pcm figure 16-1: spi module block diagram note 1: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source. to complement the inform ation in this data sheet, refer to section 23. ?serial peripheral interface (spi)? (ds61106) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. internal data bus sdix sdox ssx /f sync sckx spixsr bit 0 shift control edge select msten baud rate slave select sync control clock control transmit receive and frame note: access spixtxb and spixrxb fifos via spixbuf register. fifos share address spixbuf spixbuf generator pbclk write read spixtxb fifo spixrxb fifo refclk mclksel www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 166 preliminary ? 2011-2012 microchip technology inc. register 16-1: spixcon: spi control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 frmen frmsync frmpol mssen frmsypw frmcnt<2:0> 23:16 r/w-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 mclksel (2) ? ? ? ? ? spife enhbuf (2) 15:8 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 on (1) ? sidl dissdo mode32 mode16 smp cke (3) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ssen ckp msten dissdi stxi sel<1:0> srx isel<1:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 frmen: framed spi support bit 1 = framed spi support is enabled (ssx pin used as fsync input/output) 0 = framed spi support is disabled bit 30 frmsync: frame sync pulse direction control on ssx pin bit (framed spi mode only) 1 = frame sync pulse input (slave mode) 0 = frame sync pulse output (master mode) bit 29 frmpol: frame sync polarity bit (framed spi mode only) 1 = frame pulse is active-high 0 = frame pulse is active-low bit 28 mssen: master mode slave select enable bit 1 = slave select spi support enabled. the ss pin is automatically driven during transmission in master mode. polarity is de termined by the frmpol bit. 0 = slave select spi support is disabled. bit 27 frmsypw: frame sync pulse width bit 1 = frame sync pulse is one character wide 0 = frame sync pulse is one clock wide bit 26-24 frmcnt<2:0>: frame sync pulse counter bits. controls th e number of data characters transmitted per pulse. this bit is only valid in framed_sync mode. 111 = reserved; do not use 110 = reserved; do not use 101 = generate a frame sync pulse on every 32 data characters 100 = generate a frame sync pulse on every 16 data characters 011 = generate a frame sync pulse on every 8 data characters 010 = generate a frame sync pulse on every 4 data characters 001 = generate a frame sync pulse on every 2 data characters 000 = generate a frame sync pulse on every data character bit 23 mclksel: master clock enable bit (2) 1 = refclk is used by the baud rate generator 0 = pbclk is used by the baud rate generator bit 22-18 unimplemented: read as ? 0 ? bit 17 spife: frame sync pulse edge select bit (framed spi mode only) 1 = frame synchronization pulse coincides with the first bit clock 0 = frame synchronization pulse precedes the first bit clock note 1: when using the 1:1 pbclk divisor, the user?s software should not read or write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that clears the module?s on bit. 2: this bit can only be wri tten when the on bit = 0 . 3: this bit is not used in the framed spi mode . the user should program this bit to ? 0 ? for the framed spi mode (frmen = 1 ). www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 167 pic32mx1xx/2xx bit 16 enhbuf: enhanced buffer enable bit (2) 1 = enhanced buffer mode is enabled 0 = enhanced buffer mode is disabled bit 15 on: spi peripheral on bit (1) 1 = spi peripheral is enabled 0 = spi peripheral is disabled bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit 1 = discontinue operation when cpu enters in idle mode 0 = continue operation in idle mode bit 12 dissdo: disable sdox pin bit 1 = sdox pin is not used by the module. pin is controlled by associated port register 0 = sdox pin is controlled by the module bit 11-10 mode<32,16>: 32/16-bit communication select bits when auden = 1 : mode32 mode16 communication 11 24-bit data, 32-bit fifo, 32-bit channel/64-bit frame 10 32-bit data, 32-bit fifo, 32-bit channel/64-bit frame 01 16-bit data, 16-bit fifo, 32-bit channel/64-bit frame 00 16-bit data, 16-bit fifo, 16-bit channel/32-bit frame when auden = 0 : mode32 mode16 communication 1x 32-bit 01 16-bit 00 8-bit bit 9 smp: spi data input sample phase bit master mode (msten = 1 ): 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time slave mode (msten = 0 ): smp value is ignored when spi is used in slave mode. the module always uses smp = 0 . bit 8 cke: spi clock edge select bit (3) 1 = serial output data changes on transition from acti ve clock state to idle clock state (see ckp bit) 0 = serial output data changes on transition from idle clock state to active clock state (see ckp bit) bit 7 ssen: slave select enable (slave mode) bit 1 = ssx pin used for slave mode 0 = ssx pin not used for slave mode, pin controlled by port function. bit 6 ckp: clock polarity select bit 1 = idle state for clock is a high level; active state is a low level 0 = idle state for clock is a low level; active state is a high level bit 5 msten: master mode enable bit 1 = master mode 0 =slave mode bit 4 dissdi: disable sdi bit 1 = sdi pin is not used by the spi module (pin is controlled by port function) 0 = sdi pin is controlled by the spi module register 16-1: spixcon: spi co ntrol register (continued) note 1: when using the 1:1 pbclk divisor, the user?s software should not read or write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that clears the module?s on bit. 2: this bit can only be wri tten when the on bit = 0 . 3: this bit is not used in the framed spi mode . the user should program this bit to ? 0 ? for the framed spi mode (frmen = 1 ). www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 168 preliminary ? 2011-2012 microchip technology inc. bit 3-2 stxisel<1:0>: spi transmit buffer empty interrupt mode bits 11 = interrupt is generated when the buffer is not full (has one or more empty elements) 10 = interrupt is generated when the buffer is empty by one-half or more 01 = interrupt is generated when th e buffer is completely empty 00 = interrupt is generated when the last transfer is shifted out of spisr and transmit operations are complete bit 1-0 srxisel<1:0>: spi receive buffer full interrupt mode bits 11 = interrupt is generated when the buffer is full 10 = interrupt is generated when the buf fer is full by one-half or more 01 = interrupt is generated when the buffer is not empty 00 = interrupt is generated when the last word in th e receive buffer is read (i.e., buffer is empty) register 16-1: spixcon: spi co ntrol register (continued) note 1: when using the 1:1 pbclk divisor, the user?s software should not read or write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that clears the module?s on bit. 2: this bit can only be wri tten when the on bit = 0 . 3: this bit is not used in the framed spi mode . the user should program this bit to ? 0 ? for the framed spi mode (frmen = 1 ). www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 169 pic32mx1xx/2xx register 16-2: spixcon2: spi control register 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 spisgnext ? ? frmerren spiroven spituren ignrov igntur 7:0 r/w-0 u-0 u-0 u-0 r/w-0 u-0 r/w-0 r/w-0 auden (1) ? ? ? audmono (1,2) ? audmod<1:0> (1,2) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 spisgnext: sign extend read data from the rx fifo bit 1 = data from rx fifo is sign extended 0 = data from rx fifo is not sign extened bit 14-13 unimplemented: read as ? 0 ? bit 12 frmerren: enable interrupt events via frmerr bit 1 = frame error overflow generates error events 0 = frame error does not generate error events bit 11 spiroven: enable interrupt events via spirov bit 1 = receive overflow generates error events 0 = receive overflow does not generate error events bit 10 spituren: enable interrupt events via spitur bit 1 = transmit underrun generates error events 0 = transmit underrun does not generates error events bit 9 ignrov: ignore receive overflow bit (for audio data transmissions) 1 = a rov is not a critical error; during rov data in the fifo is not overwritten by receive data 0 = a rov is a critical error which stop spi operation bit 8 igntur: ignore transmit underrun bit (for audio data transmissions) 1 = a tur is not a critical error and zeros ar e transmitted until the spixtxb is not empty 0 = a tur is a critical error which stop spi operation bit 7 auden: enable audio codec support bit (1) 1 = audio protocol enabled 0 = audio protocol disabled bit 6-5 unimplemented: read as ? 0 ? bit 3 audmono: transmit audio data format bit (1,2) 1 = audio data is mono (each data word is transmitted on both left and right channels) 0 = audio data is stereo bit 2 unimplemented: read as ? 0 ? bit 1-0 audmod<1:0>: audio protocol mode bit (1,2) 11 = pcm/dsp mode 10 = right justified mode 01 = left justified mode 00 = i 2 s mode note 1: this bit can only be wri tten when the on bit = 0 . 2: this bit is only valid for auden = 1 . www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 170 preliminary ? 2011-2012 microchip technology inc. register 16-3: spixstat: spi status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 r-0 r-0 r-0 r-0 r-0 ? ? ? rxbufelm<4:0> 23:16 u-0 u-0 u-0 r-0 r-0 r-0 r-0 r-0 ? ? ? txbufelm<4:0> 15:8 u-0 u-0 u-0 r/c-0, hs r-0 u-0 u-0 r-0 ? ? ? frmerr spibusy ? ?spitur 7:0 r-0 r/w-0 r-0 u-0 r-1 u-0 r-0 r-0 srmt spirov spirbe ?spitbe ? spitbf spirbf legend: c = clearable bit hs = set in hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-29 unimplemented: read as ? 0 ? bit 28-24 rxbufelm<4:0>: receive buffer element count bits (valid only when enhbuf = 1 ) bit 23-21 unimplemented: read as ? 0 ? bit 20-16 txbufelm<4:0>: transmit buffer element count bits (valid only when enhbuf = 1 ) bit 15-13 unimplemented: read as ? 0 ? bit 12 frmerr: spi frame error status bit 1 = frame error detected 0 = no frame error detected this bit is only valid when frmen = 1 . bit 11 spibusy: spi activity status bit 1 = spi peripheral is currently busy with some transactions 0 = spi peripheral is currently idle bit 10-9 unimplemented: read as ? 0 ? bit 8 spitur: transmit under run bit 1 = transmit buffer has encountered an underrun condition 0 = transmit buffer has no underrun condition this bit is only valid in framed sync mode; the underrun condition must be cleared by disabling/re-enabling the module. bit 7 srmt: shift register empty bit (valid only when enhbuf = 1 ) 1 = when spi module shift register is empty 0 = when spi module shift register is not empty bit 6 spirov: receive overflow flag bit 1 = a new data is completely received and discarded. the user software has not read the previous data in the spixbuf register. 0 = no overflow has occurred this bit is set in hardware; can only be cleared (= 0 ) in software. bit 5 spirbe: rx fifo empty bit (valid only when enhbuf = 1 ) 1 = rx fifo is empty (crptr = swptr) 0 = rx fifo is not empty (crptr swptr) bit 4 unimplemented: read as ? 0 ? www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 171 pic32mx1xx/2xx bit 3 spitbe: spi transmit buffer empty status bit 1 = transmit buffer, spixtxb is empty 0 = transmit buffer, spixtxb is not empty automatically set in hardware when spi tr ansfers data from spixtxb to spixsr. automatically cleared in hardware when spixbuf is written to, loading spixtxb. bit 2 unimplemented: read as ? 0 ? bit 1 spitbf: spi transmit buffer full status bit 1 = transmit not yet started, spitxb is full 0 = transmit buffer is not full standard buffer mode: automatically set in hardware when the core writes to the spi buf location, loading spitxb. automatically cleared in hardware when the spi module transfers data from spitxb to spisr. enhanced buffer mode: set when cwptr + 1 = srptr; cleared otherwise bit 0 spirbf: spi receive buffer full status bit 1 = receive buffer, spixrxb is full 0 = receive buffer, spixrxb is not full standard buffer mode: automatically set in hardware when the spi module transfers data from spixsr to spixrxb. automatically cleared in hardware when spixbuf is read from, reading spixrxb. enhanced buffer mode: set when swptr + 1 = crptr; cleared otherwise register 16-3: spixstat: spi status register www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 172 preliminary ? 2011-2012 microchip technology inc. notes: www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 173 pic32mx1xx/2xx 17.0 inter-integrated circuit? (i 2 c?) the i 2 c module provides complete hardware support for both slave and multi-master modes of the i 2 c serial communication standard. figure 17-1 illustrates the i 2 c module block diagram. each i 2 c module has a 2-pin interface: the sclx pin is clock and the sdax pin is data. each i 2 c module offers the fo llowing key features: ?i 2 c interface supporting both master and slave operation ?i 2 c slave mode supports 7-bit and 10-bit addressing ?i 2 c master mode supports 7-bit and 10-bit addressing ?i 2 c port allows bidirectional transfers between master and slaves ? serial clock synchronization for the i 2 c port can be used as a handshake mechanism to suspend and resume serial transfer (sclrel control) ?i 2 c supports multi-master operation; detects bus collision and arbitrates accordingly ? provides support for address bit masking note 1: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 24. ?inter- integrated circuit? (i 2 c?)? (ds61116) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 174 preliminary ? 2011-2012 microchip technology inc. figure 17-1: i 2 c? block diagram internal data bus sclx sdax shift match detect i2cxadd start and stop bit detect clock address match clock stretching i2cxtrn lsb shift clock brg down counter reload control pbclk start and stop bit generation acknowledge generation collision detect i2cxcon i2cxstat control logic read lsb write read i2cxbrg i2cxrsr write read write read write read write read write read i2cxmsk i2cxrcv www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 175 pic32mx1xx/2xx register 17-1: i2c x con: i 2 c? control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 r/w-1, hc r/w-0 r/w-0 r/w-0 r/w-0 on (1) ? sidl sclrel strict a10m disslw smen 7:0 r/w-0 r/w-0 r/w-0 r/w-0, hc r/w-0, hc r/w-0, hc r/w- 0, hc r/w-0, hc gcen stren ackdt acken rcen pen rsen sen legend: hc = cleared in hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: i 2 c enable bit (1) 1 = enables the i 2 c module and configures the sda and scl pins as serial port pins 0 = disables the i 2 c module; all i 2 c pins are controlled by port functions bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12 sclrel: sclx release control bit (when operating as i 2 c slave) 1 = release sclx clock 0 = hold sclx clock low (clock stretch) if stren = 1 : bit is r/w (i.e., software can write ? 0 ? to initiate stretch and write ? 1 ? to release clock). hardware clear at beginning of slave transmission. hardwa re clear at end of slave reception. if stren = 0 : bit is r/s (i.e., software can only write ? 1 ? to release clock). hardware clear at beginning of slave transmission. bit 11 strict: strict i 2 c reserved address rule enable bit 1 = strict reserved addressing is enforced. device does not respond to reserved address space or generate addresses in reserved address space. 0 = strict i 2 c reserved address rule not enabled bit 10 a10m: 10-bit slave address bit 1 = i2cxadd is a 10-bit slave address 0 = i2cxadd is a 7-bit slave address bit 9 disslw: disable slew rate control bit 1 = slew rate control disabled 0 = slew rate control enabled bit 8 smen: smbus input levels bit 1 = enable i/o pin thresholds compliant with smbus specification 0 = disable smbus input thresholds note 1: when using 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 176 preliminary ? 2011-2012 microchip technology inc. bit 7 gcen: general call enable bit (when operating as i 2 c slave) 1 = enable interrupt when a general call address is received in the i2cxrsr (module is enabled for reception) 0 = general call address disabled bit 6 stren: sclx clock stretch enable bit (when operating as i 2 c slave) used in conjunction with sclrel bit. 1 = enable software or receive clock stretching 0 = disable software or receive clock stretching bit 5 ackdt: acknowledge data bit (when operating as i 2 c master, applicable during master receive) value that is transmitted when the soft ware initiates an acknowledge sequence. 1 = send nack during acknowledge 0 = send ack during acknowledge bit 4 acken: acknowledge sequence enable bit (when operating as i 2 c master, applicable during master receive) 1 = initiate acknowledge sequence on sdax and sclx pins and transmit ackdt data bit. hardware clear at end of ma ster acknowledge sequence. 0 = acknowledge sequence not in progress bit 3 rcen: receive enable bit (when operating as i 2 c master) 1 = enables receive mode for i 2 c. hardware clear at end of eighth bit of master receive data byte. 0 = receive sequence not in progress bit 2 pen: stop condition enable bit (when operating as i 2 c master) 1 = initiate stop condition on sdax and sclx pins. hardware clear at end of master stop sequence. 0 = stop condition not in progress bit 1 rsen: repeated start condition enable bit (when operating as i 2 c master) 1 = initiate repeated start condition on sdax and sclx pins. hardware clear at end of master repeated start sequence. 0 = repeated start condition not in progress bit 0 sen: start condition enable bit (when operating as i 2 c master) 1 = initiate start condition on sdax and sclx pins. hardware clear at end of master start sequence. 0 = start condition not in progress register 17-1: i2c x con: i 2 c? control register (continued) note 1: when using 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 177 pic32mx1xx/2xx register 17-2: i2c x stat: i 2 c? status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r-0, hsc r-0, hsc u-0 u-0 u-0 r/ c-0, hs r-0, hsc r-0, hsc ackstat trstat ? ? ? bcl gcstat add10 7:0 r/c-0, hs r/c-0, hs r-0, hsc r/c-0, hsc r/c-0, hsc r-0, hsc r-0, hsc r-0, hsc iwcol i2cov d_a p s r_w rbf tbf legend: hs = set in hardware hsc = hardware set/cleared r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared c = clearable bit bit 31-16 unimplemented: read as ? 0 ? bit 15 ackstat: acknowledge status bit (when operating as i 2 c? master, applicable to master transmit operation) 1 = nack received from slave 0 = ack received from slave hardware set or clear at end of slave acknowledge. bit 14 trstat: transmit status bit (when operating as i 2 c master, applicable to master transmit operation) 1 = master transmit is in progress (8 bits + ack) 0 = master transmit is not in progress hardware set at beginning of master transmission. hardware clear at end of slave acknowledge. bit 13-11 unimplemented: read as ? 0 ? bit 10 bcl: master bus collision detect bit 1 = a bus collision has been detec ted during a master operation 0 = no collision hardware set at detection of bus collision. bit 9 gcstat: general call status bit 1 = general call address was received 0 = general call address was not received hardware set when address matches general call address. hardware clear at stop detection. bit 8 add10: 10-bit address status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched hardware set at match of 2nd byte of matched 10 -bit address. hardware clear at stop detection. bit 7 iwcol: write collision detect bit 1 = an attempt to write the i2cx trn register failed because the i 2 c module is busy 0 = no collision hardware set at occurrence of write to i2cxtrn while busy (cleared by software). bit 6 i2cov: receive overflow flag bit 1 = a byte was received while the i2cxrcv re gister is still holding the previous byte 0 = no overflow hardware set at attempt to transfer i2cxrsr to i2cx rcv (cleared by software). bit 5 d_a: data/address bit (when operating as i 2 c slave) 1 = indicates that the last byte received was data 0 = indicates that the last byte received was device address hardware clear at device address match. hardware set by reception of slave byte. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 178 preliminary ? 2011-2012 microchip technology inc. bit 4 p: stop bit 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last hardware set or clear when start, repeated start or stop detected. bit 3 s: start bit 1 = indicates that a start (or repeated start) bit has been detected last 0 = start bit was not detected last hardware set or clear when start, repeated start or stop detected. bit 2 r_w: read/write information bit (when operating as i 2 c slave) 1 = read ? indicates data transfer is output from slave 0 = write ? indicates data transfer is input to slave hardware set or clear after reception of i 2 c device address byte. bit 1 rbf: receive buffer full status bit 1 = receive complete, i2cxrcv is full 0 = receive not complete, i2cxrcv is empty hardware set when i2cxrcv is written with received byte. hardware clear when software reads i2cxrcv. bit 0 tbf: transmit buffer full status bit 1 = transmit in progress, i2cxtrn is full 0 = transmit complete, i2cxtrn is empty hardware set when software writes i2cxtrn. hard ware clear at completion of data transmission. register 17-2: i2c x stat: i 2 c? status register (continued) www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 179 pic32mx1xx/2xx 18.0 universal asynchronous receiver transmitter (uart) the uart module is one of the serial i/o modules available in pic32mx1xx/2xx family devices. the uart is a full-duplex, asynchronous communication channel that communicates with peripheral devices and personal computers through protocols, such as rs-232, rs-485, lin and irda ? . the module also sup- ports the hardware flow control option, with uxcts and uxrts pins, and also includes an irda encoder and decoder. the primary features of the uart module are: ? full-duplex, 8-bit or 9-bit data transmission ? even, odd or no parity options (for 8-bit data) ? one or two stop bits ? hardware auto-baud feature ? hardware flow control option ? fully integrated baud ra te generator (brg) with 16-bit prescaler ? baud rates ranging from 38 bps to 10 mbps at 40 mhz ? 8-level deep first-in-first-out (fifo) transmit data buffer ? 8-level deep fifo receive data buffer ? parity, framing and buffer overrun error detection ? support for interrupt-only on address detect (9th bit = 1 ) ? separate transmit and receive interrupts ? loopback mode for diagnostic support ? lin protocol support ? irda encoder and decoder with 16x baud clock output for external irda encoder/decoder support figure 18-1 illustrates a simplified block diagram of the uart. figure 18-1: uart simplified block diagram note 1: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 21. ?universal asynchronous receiver transmitter (uart)? (ds61107) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. baud rate generator uxrx hardware flow control uartx receiver uartx transmitter uxtx uxcts uxrts / bclkx irda ? note: not all pins are available for all uart modules. refer to the device-specific pin di agram for more information. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 180 preliminary ? 2011-2012 microchip technology inc. register 18-1: uxmode: uartx mode register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 on (1) ?sidlirenrtsmd ?uen<1:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wake lpback abaud rxinv brgh pdsel<1:0> stsel legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: uartx enable bit (1) 1 = uartx is enabled. uartx pins are controlled by uartx as defined by uen<1:0> and utxen control bits 0 = uartx is disabled. all uartx pins are controlled by corresponding bits in the portx, trisx and latx registers; uartx power consumption is minimal bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit 1 = discontinue operation when device enters idle mode 0 = continue operation in idle mode bit 12 iren: irda encoder and decoder enable bit 1 = irda is enabled 0 = irda is disabled bit 11 rtsmd: mode selection for uxrts pin bit 1 =uxrts pin is in simplex mode 0 =uxrts pin is in flow control mode bit 10 unimplemented: read as ? 0 ? bit 9-8 uen<1:0>: uartx enable bits 11 = uxtx, uxrx and uxbclk pins are enabled and used; uxcts pin is controlled by corresponding bits in the portx register 10 = uxtx, uxrx, uxcts and uxrts pins are enabled and used 01 = uxtx, uxrx and uxrts pins are enabled and used; uxcts pin is controlled by corresponding bits in the portx register 00 = uxtx and uxrx pins are enabled and used; uxcts and uxrts /uxbclk pins are controlled by corresponding bits in the portx register bit 7 wake: enable wake-up on start bit detect during sleep mode bit 1 = wake-up enabled 0 = wake-up disabled bit 6 lpback: uartx loopback mode select bit 1 = loopback mode is enabled 0 = loopback mode is disabled note 1: when using 1:1 pbclk divisor, the user software should not read/write the peripheral sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 181 pic32mx1xx/2xx bit 5 abaud: auto-baud enable bit 1 = enable baud rate measurement on the next characte r ? requires reception of sync character (0x55); cleared by hardware upon completion 0 = baud rate measurement disabled or completed bit 4 rxinv: receive polarity inversion bit 1 = uxrx idle state is ? 0 ? 0 = uxrx idle state is ? 1 ? bit 3 brgh: high baud rate enable bit 1 = high-speed mode ? 4x baud clock enabled 0 = standard speed mode ? 16x baud clock enabled bit 2-1 pdsel<1:0>: parity and data selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 stsel: stop selection bit 1 = 2 stop bits 0 = 1 stop bit register 18-1: uxmode: uartx mode register (continued) note 1: when using 1:1 pbclk divisor, the user software should not read/write the peripheral sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 182 preliminary ? 2011-2012 microchip technology inc. register 18-2: uxsta: uartx status and control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ?adm_en 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 addr<7:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-1 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt 7:0 r/w-0 r/w-0 r/w-0 r-1 r-0 r-0 r/w-0 r-0 urxisel<1:0> adden ridle perr ferr oerr urxda legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-25 unimplemented: read as ? 0 ? bit 24 adm_en: automatic address detect mode enable bit 1 = automatic address detect mode is enabled 0 = automatic address detect mode is disabled bit 23-16 addr<7:0>: automatic address mask bits when the adm_en bit is ? 1 ?, this value defines the address character to use for automatic address detection. bit 15-14 utxisel<1:0>: tx interrupt mode selection bits 11 = reserved, do not use 10 = interrupt is generated and asserted while the transmit buffer is empty 01 = interrupt is generated and asserted w hen all characters have been transmitted 00 = interrupt is generated and asserted while the transmit buffer contains at least one empty space bit 13 utxinv: transmit polarity inversion bit if irda mode is disabled (i.e., iren (uxmode<12>) is ? 0 ?): 1 = uxtx idle state is ? 0 ? 0 = uxtx idle state is ? 1 ? if irda mode is enabled (i.e., iren (uxmode<12>) is ? 1 ?): 1 = irda encoded uxtx idle state is ? 1 ? 0 = irda encoded uxtx idle state is ? 0 ? bit 12 urxen: receiver enable bit 1 = uartx receiver is enabled. uxrx pin is controlled by uartx (if on = 1 ) 0 = uartx receiver is disabled. uxrx pin is ignored by the uartx module. uxrx pin is controlled by port. bit 11 utxbrk: transmit break bit 1 = send break on next transmission. start bit followed by twelve ? 0 ? bits, followed by stop bit; cleared by hardware upon completion 0 = break transmission is disabled or completed bit 10 utxen: transmit enable bit 1 = uartx transmitter is enabled. uxtx pin is controlled by uartx (if on = 1 ) 0 = uartx transmitter is disabled. any pending transmi ssion is aborted and buffer is reset. uxtx pin is con- trolled by port. bit 9 utxbf: transmit buffer full status bit (read-only) 1 = transmit buffer is full 0 = transmit buffer is not full, at le ast one more character can be written bit 8 trmt: transmit shift register is empty bit (read-only) 1 = transmit shift register is empty and transmit buf fer is empty (the last transmission has completed) 0 = transmit shift register is not empty, a transmi ssion is in progress or queued in the transmit buffer www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 183 pic32mx1xx/2xx bit 7-6 urxisel<1:0>: receive interrupt mode selection bit 11 = reserved; do not use 10 = interrupt flag bit is asserted while receive buffer is 3/4 or more full (i.e., has 6 or more data characters) 01 = interrupt flag bit is asserted while receive buffer is 1/2 or more full (i.e., has 4 or more data characters) 00 = interrupt flag bit is asserted while receive buffer is not empty (i.e., has at least 1 data character) bit 5 adden: address character detect bit (bit 8 of received data = 1 ) 1 = address detect mode is enabled. if 9-bit mode is not selected, this control bit has no effect 0 = address detect mode is disabled bit 4 ridle: receiver idle bit (read-only) 1 = receiver is idle 0 = data is being received bit 3 perr: parity error status bit (read-only) 1 = parity error has been detected for the current character 0 = parity error has not been detected bit 2 ferr: framing error status bit (read-only) 1 = framing error has been detected for the current character 0 = framing error has not been detected bit 1 oerr: receive buffer overrun error status bit. this bit is set in hardware and can only be cleared (= 0 ) in software. clearing a previously set oerr bit resets the receiver buffer and rsr to empty state. 1 = receive buffer has overflowed 0 = receive buffer has not overflowed bit 0 urxda: receive buffer data available bit (read-only) 1 = receive buffer has data, at least one more character can be read 0 = receive buffer is empty register 18-2: uxsta: uartx status and control register (continued) www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 184 preliminary ? 2011-2012 microchip technology inc. figure 18-2 and figure 18-3 illustrate typical receive and transmit timing for the uart module. figure 18-2: uart reception figure 18-3: transmission (8-bit or 9-bit data) start 1 stop start 2 stop 4 start 5 stop 10 start 11 stop 13 read to uxrxreg uxrx ridle oerr uxrxif urxisel = 00 uxrxif urxisel = 01 uxrxif urxisel = 10 char 1 char 2-4 char 5-10 char 11-13 cleared by software cleared by software cleared by software start start bit 0 bit 1 stop write to tsr bclk/16 (shift clock) uxtx uxtxif uxtxif utxisel = 00 bit 1 uxtxreg utxisel = 01 uxtxif utxisel = 10 8 into txbuf pull from buffer www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 185 pic32mx1xx/2xx 19.0 parallel master port (pmp) the pmp is a parallel 8-bit input/output module specifically designed to communicate with a wide variety of parallel devices, such as communications peripherals, lcds, external memory devices and microcontrollers. because the interface to parallel peripherals varies significantly, the pmp module is highly configurable. key features of the pmp module include: ? fully multiplexed address/data mode ? demultiplexed or partially multiplexed address/ data mode - up to 11 address lines with single chip select - up to 12 address lines without chip select ? one chip select line ? programmable strobe options - individual read and write strobes or; - read/write strobe with enable strobe ? address auto-increment/auto-decrement ? programmable address/data multiplexing ? programmable polarity on control signals ? legacy parallel slave port support ? enhanced parallel slave support - address support - 4-byte deep auto-incrementing buffer ? programmable wait states ? selectable input voltage levels figure 19-1: pmp module pinout and connections to external devices note 1: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 13. ?parallel master port (pmp)? (ds61128) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. pma<0> pma<14> pmrd pmwr pmenb pmrd/pmwr pmcs1 pma<1> pma<10:2> pmall pmalh flash address bus data bus control lines pic32mx1xx/2xx lcd fifo microcontroller 8-bit data (with or without multiplexed addressing) up to 12-bit address parallel buffer pmd<7:0> master port eeprom sram www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 186 preliminary ? 2011-2012 microchip technology inc. register 19-1: pmcon: parall el port control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 on (1) ?sidl adrmux<1:0> pmpttl ptwren ptrden 7:0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 r/w-0 r/w-0 csf<1:0> (2) alp (2) ?cs1p (2) ? wrsp rdsp legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: parallel master port enable bit (1) 1 = pmp enabled 0 = pmp disabled, no off-chip access performed bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-11 adrmux<1:0>: address/data multiplexing selection bits 11 = lower 8 bits of address are multiplexed on pmd<7:0> pins; upper 8 bits are not used 10 = all 16 bits of address are multiplexed on pmd<7:0> pins 01 = lower 8 bits of address are multiplexed on pmd<7:0> pins, upper bits are on pma<10:8> and pma<14> 00 = address and data appear on separate pins bit 10 pmpttl: pmp module ttl input buffer select bit 1 = pmp module uses ttl input buffers 0 = pmp module uses schmitt trigger input buffer bit 9 ptwren: write enable strobe port enable bit 1 = pmwr/pmenb port enabled 0 = pmwr/pmenb port disabled bit 8 ptrden: read/write strobe port enable bit 1 = pmrd/pmwr port enabled 0 = pmrd/pmwr port disabled bit 7-6 csf<1:0>: chip select function bits (2) 11 = reserved 10 = pmcs1 function as chip select 01 = pmcs1 functions as address bit 14 00 = pmcs1 function as address bit 14 bit 5 alp: address latch polarity bit (2) 1 = active-high (pmall and pmalh) 0 = active-low (pmall and pmalh ) note 1: when using 1:1 pbclk divisor, the user?s software s hould not read/write the peripheral?s sfrs in the sysclk cycle immediately followin g the instruction that clears the module?s on control bit. 2: these bits have no effect when their corresponding pins are used as address lines. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 187 pic32mx1xx/2xx bit 4 unimplemented: read as ? 0 ? bit 3 cs1p: chip select 0 polarity bit (2) 1 = active-high (pmcs1) 0 = active-low (pmcs1 ) bit 2 unimplemented: read as ? 0 ? bit 1 wrsp: write strobe polarity bit for slave modes and master mode 2 (pmmode<9:8> = 00 , 01 , 10 ) : 1 = write strobe active-high (pmwr) 0 = write strobe active-low (pmwr ) for master mode 1 (pmmode<9:8> = 11 ) : 1 = enable strobe active-high (pmenb) 0 = enable strobe active-low (pmenb ) bit 0 rdsp: read strobe polarity bit for slave modes and master mode 2 (pmmode<9:8> = 00 , 01 , 10 ) : 1 = read strobe active-high (pmrd) 0 = read strobe active-low (pmrd ) for master mode 1 (pmmode<9:8> = 11 ) : 1 = read/write strobe active-high (pmrd/pmwr ) 0 = read/write strobe active-low (pmrd /pmwr) register 19-1: pmcon: parallel po rt control register (continued) note 1: when using 1:1 pbclk divisor, the user?s software s hould not read/write the peripheral?s sfrs in the sysclk cycle immediately followin g the instruction that clears the module?s on control bit. 2: these bits have no effect when their corresponding pins are used as address lines. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 188 preliminary ? 2011-2012 microchip technology inc. register 19-2: pmmode: parallel port mode register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 busy irqm<1:0> incm<1:0> ? mode<1:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 waitb<1:0> (1) waitm<3:0> (1) waite<1:0> (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 busy: busy bit (master mode only) 1 = port is busy 0 = port is not busy bit 14-13 irqm<1:0>: interrupt request mode bits 11 = reserved, do not use 10 = interrupt generated when read buffer 3 is read or write buffer 3 is written (buffered psp mode) or on a read or write operation when pma<1:0> = 11 (addressable slave mode only) 01 = interrupt generated at the end of the read/write cycle 00 = no interrupt generated bit 12-11 incm<1:0>: increment mode bits 11 = slave mode read and write buffers auto-increment (pmmode<1:0> = 00 only) 10 = decrement addr<10:2> and addr <14> by 1 every read/write cycle (2) 01 = increment addr<10:2> and addr< 14> by 1 every read/write cycle (2) 00 = no increment or decrement of address bit 10 unimplemented: read as ? 0 ? bit 9-8 mode<1:0>: parallel port mode select bits 11 = master mode 1 (pmcs1, pmrd/pmwr, pmenb, pma , and pmd<7:0>) 10 = master mode 2 (pmcs1, pmrd, pmwr, pma, and pmd<7:0>) 01 = enhanced slave mode, control signals (pm rd, pmwr, pmcs1, pmd<7:0>, and pma<1:0>) 00 = legacy parallel slave port, control si gnals (pmrd, pmwr, pmcs1, and pmd<7:0>) bit 7-6 waitb<1:0>: data setup to read/write strobe wait states bits (1) 11 = data wait of 4 t pb ; multiplexed address phase of 4 t pb 10 = data wait of 3 t pb ; multiplexed address phase of 3 t pb 01 = data wait of 2 t pb ; multiplexed address phase of 2 t pb 00 = data wait of 1 t pb ; multiplexed address phase of 1 t pb (default) note 1: whenever waitm<3:0> = 0000, waitb and waite bits are ignored and forced to 1 t pbclk cycle for a write operation; waitb = 1 t pbclk cycle, waite = 0 t pbclk cycles for a read operation. 2: address bit a14 is not subject to auto-increment /decrement if configured as chip select cs1. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 189 pic32mx1xx/2xx bit 5-2 waitm<3:0>: data read/write strobe wait states bits (1) 1111 = wait of 16 t pb ? ? ? 0001 = wait of 2 t pb 0000 = wait of 1 t pb (default) bit 1-0 waite<1:0>: data hold after read/write strobe wait states bits (1) 11 = wait of 4 t pb 10 = wait of 3 t pb 01 = wait of 2 t pb 00 = wait of 1 t pb (default) for read operations: 11 = wait of 3 t pb 10 = wait of 2 t pb 01 = wait of 1 t pb 00 = wait of 0 t pb (default) register 19-2: pmmode: parallel port mode register (continued) note 1: whenever waitm<3:0> = 0000, waitb and waite bits are ignored and forced to 1 t pbclk cycle for a write operation; waitb = 1 t pbclk cycle, waite = 0 t pbclk cycles for a read operation. 2: address bit a14 is not subject to auto-increment /decrement if configured as chip select cs1. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 190 preliminary ? 2011-2012 microchip technology inc. register 19-3: pmaddr: para llel port address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ?cs1 ? ? ? addr<10:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 addr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-15 unimplemented: read as ? 0 ? bit 14 cs1: chip select 1 bit 1 = chip select 1 is active 0 = chip select 1 is inactive (pin functions as pma<14>) bit 13-11 unimplemented: read as ? 0 ? bit 10-0 addr<10:0>: destination address bits www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 191 pic32mx1xx/2xx register 19-4: pmaen: paralle l port pin enable register (1,2) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ?pten14 ? ? ?pten<10:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pten<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-15 unimplemented: read as ? 0 ? bit 15-14 pten14: pmcs1 strobe enable bits 1 = pma14 functions as either pma14 or pmcs1 (1) 0 = pma14 functions as port i/o bit 13-11 unimplemented: read as ? 0 ? bit 10-2 pten<10:2>: pmp address port enable bits 1 = pma<10:2> function as pmp address lines 0 = pma<10:2> function as port i/o bit 1-0 pten<1:0>: pmalh/pmall strobe enable bits 1 = pma1 and pma0 function as either pma<1:0> or pmalh and pmall (2) 0 = pma1 and pma0 pads functions as port i/o note 1: the use of this pin as pma14 or cs1 is selected by the csf<1:0> bits in the pmcon register. 2: the use of these pins as pma1/pma0 or pmalh/ pmall depends on the address/data multiplex mode selected by bits adrmux<1:0> in the pmcon register. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 192 preliminary ? 2011-2012 microchip technology inc. register 19-5: pmstat: parallel port status register (slave modes only) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r-0 r/w-0, hsc u-0 u-0 r-0 r-0 r-0 r-0 ibf ibov ? ? ib3fib2fib1fib0f 7:0 r-1 r/w-0, hsc u-0 u-0 r-1 r-1 r-1 r-1 obe obuf ? ? ob3e ob2e ob1e ob0e legend: hsc = set by hardware; cleared by software r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 ibf: input buffer full status bit 1 = all writable input buffer registers are full 0 = some or all of the writable input buffer registers are empty bit 14 ibov: input buffer overflow status bit 1 = a write attempt to a full input byte buffer occurred (must be cleared in software) 0 = no overflow occurred bit 13-12 unimplemented: read as ? 0 ? bit 11-8 ibxf: input buffer x status full bits 1 = input buffer contains data that has not been read (reading buffer will clear this bit) 0 = input buffer does not contain any unread data bit 7 obe: output buffer empty status bit 1 = all readable output buffer registers are empty 0 = some or all of the readable output buffer registers are full bit 6 obuf: output buffer underflow status bit 1 = a read occurred from an empty output byte buffer (must be cleared in software) 0 = no underflow occurred bit 5-4 unimplemented: read as ? 0 ? bit 3-0 obxe: output buffer x status empty bits 1 = output buffer is empty (writing data to the buffer will clear this bit) 0 = output buffer contains data that has not been transmitted www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 193 pic32mx1xx/2xx 20.0 real-time clock and calendar (rtcc) the pic32 rtcc module is intended for applications in which accurate time must be maintained for extended periods of time with minimal or no cpu intervention. low-power optimization provides extended battery lifetime while keeping track of time. following are some of the key features of this module: ? time: hours, minutes and seconds ? 24-hour format (military time) ? visibility of one-half second period ? provides calendar: weekday, date, month and year ? alarm intervals are configurable for half of a second, one second, 10 seconds, one minute, 10 minutes, one hour, one day, one week, one month and one year ? alarm repeat with decrementing counter ? alarm with indefinite repeat: chime ? year range: 2000 to 2099 ? leap year correction ? bcd format for smalle r firmware overhead ? optimized for long-term battery operation ? fractional second synchronization ? user calibration of the clock crystal frequency with auto-adjust ? calibration range: 0.66 seconds error per month ? calibrates up to 260 ppm of crystal error ? requirements: external 32.768 khz clock crystal ? alarm pulse or seconds clock output on rtcc pin figure 20-1: rtcc block diagram note 1: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 29. ?real-time clock and calendar (rtcc)? (ds61125) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. rtcc prescalers rtcc timer comparator compare registers repeat counter alrmtime hr, min, sec alrmdate with masks rtcc interrupt logic alarm event 32.768 khz input from secondary 0.5s alarm pulse set rtcc flag rtcval alrmval rtcc rtcoe oscillator (s osc ) cal<9:0> month, day, wday rtctime hr, min, sec rtcdate year, month, day, wday seconds pulse rtsecsel 0 1 www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 194 preliminary ? 2011-2012 microchip technology inc. register 20-1: rtccon: rtc control register (1) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ?cal<9:8> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cal<7:0> 15:8 r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 on (2,3) ?sidl ? ? ? ? ? 7:0 r/w-0 r-0 u-0 u-0 r/w-0 r-0 r-0 r/w-0 rtsecsel (4) rtcclkon ? ?rtcwren (5) rtcsync halfsec (6) rtcoe legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-26 unimplemented: read as ? 0 ? bit 25-16 cal<9:0>: rtc drift calibration bits, which contain a signed 10-bit integer value 0111111111 = maximum positive adjustment, adds 511 rtc clock pulses every one minute ? ? ? 0000000001 = minimum positive adjustment, adds 1 rtc clock pulse every one minute 0000000000 = no adjustment 1111111111 = minimum negative adjustment, subtra cts 1 rtc clock pulse every one minute ? ? ? 1000000000 = minimum negative adjustment, subtra cts 512 clock pulses every one minute bit 15 on: rtcc on bit (2,3) 1 = rtcc module is enabled 0 = rtcc module is disabled bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit 1 = disables the pbclk to the rtcc when cpu enters in idle mode 0 = continue normal operation in idle mode bit 12-8 unimplemented: read as ? 0 ? bit 7 rtsecsel: rtcc seconds clock output select bit (4) 1 = rtcc seconds clock is selected for the rtcc pin 0 = rtcc alarm pulse is selected for the rtcc pin bit 6 rtcclkon: rtcc clock enable status bit 1 = rtcc clock is actively running 0 = rtcc clock is not running bit 5-4 unimplemented: read as ? 0 ? note 1: this register is reset only on a power-on reset (por). 2: the on bit is only writable when rtcwren = 1 . 3: when using the 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 4: requires rtcoe = 1 (rtccon<0>) for the output to be active. 5: the rtcwren bit can be set only when the write sequence is enabled. 6: this bit is read-only. it is cleared to ? 0 ? on a write to the seconds bit fields (rtctime<14:8>). www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 195 pic32mx1xx/2xx bit 3 rtcwren: rtc value registers write enable bit (5) 1 = rtc value registers can be written to by the user 0 = rtc value registers are locked out from being written to by the user bit 2 rtcsync: rtcc value registers read synchronization bit 1 = rtc value registers can change while reading, due to a rollover ripple that results in an invalid data read if the register is read twice and results in th e same data, the data can be assumed to be valid 0 = rtc value registers can be read wi thout concern about a rollover ripple bit 1 halfsec: half-second status bit (6) 1 = second half period of a second 0 = first half period of a second bit 0 rtcoe: rtcc output enable bit 1 = rtcc clock output enabled ? clock presented onto an i/o 0 = rtcc clock output disabled register 20-1: rtccon: rtc control register (1) (continued) note 1: this register is reset only on a power-on reset (por). 2: the on bit is only writable when rtcwren = 1 . 3: when using the 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 4: requires rtcoe = 1 (rtccon<0>) for the output to be active. 5: the rtcwren bit can be set only when the write sequence is enabled. 6: this bit is read-only. it is cleared to ? 0 ? on a write to the seconds bit fields (rtctime<14:8>). www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 196 preliminary ? 2011-2012 microchip technology inc. register 20-2: rtcalrm: rtc alarm control register (1) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 alrmen (2,3) chime (3) piv (3) alrmsync (4) amask<3:0> (3) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 arpt<7:0> (3) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 alrmen: alarm enable bit (2,3) 1 = alarm is enabled 0 = alarm is disabled bit 14 chime: chime enable bit (3) 1 = chime is enabled ? arpt<7:0> is allowed to rollover from 0x00 to 0xff 0 = chime is disabled ? arpt<7:0> stops once it reaches 0x00 bit 13 piv: alarm pulse initial value bit (3) when alrmen = 0 , piv is writable and determines the initial value of the alarm pulse. when alrmen = 1 , piv is read-only and returns the state of the alarm pulse. bit 12 alrmsync: alarm sync bit (4) 1 = arpt<7:0> and alrmen may change as a result of a half second rollover during a read. the arpt must be read repeatedly until the same valu e is read twice. this must be done since multiple bits may be changing, which are then synchronized to the pb clock domain 0 = arpt<7:0> and alrmen can be read without concer ns of rollover because the prescaler is > 32 rtc clocks away from a half-second rollover bit 11-8 amask<3:0>: alarm mask configuration bits (3) 0000 = every half-second 0001 = every second 0010 = every 10 seconds 0011 = every minute 0100 = every 10 minutes 0101 = every hour 0110 = once a day 0111 = once a week 1000 = once a month 1001 = once a year (except when configured for february 29, once every four years) 1010 = reserved; do not use 1011 = reserved; do not use 11xx = reserved; do not use note 1: this register is reset only on a power-on reset (por). 2: hardware clears the alrmen bit anytime the alarm event occurs, when arpt<7:0> = 00 and chime = 0 . 3: this field should not be written when the rtcc on bit = ? 1 ? (rtccon<15>) and alrmsync = 1 . 4: this assumes a cpu read will execute in less than 32 pbclks. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 197 pic32mx1xx/2xx bit 7-0 arpt<7:0>: alarm repeat counter value bits (3) 11111111 = alarm will trigger 256 times ? ? ? 00000000 = alarm will trigger one time the counter decrements on any alarm event. the counte r only rolls over from 0x00 to 0xff if chime = 1 . register 20-2: rtcalrm: rtc alarm control register (1) (continued) note 1: this register is reset only on a power-on reset (por). 2: hardware clears the alrmen bit anytime the alarm event occurs, when arpt<7:0> = 00 and chime = 0 . 3: this field should not be written when the rtcc on bit = ? 1 ? (rtccon<15>) and alrmsync = 1 . 4: this assumes a cpu read will execute in less than 32 pbclks. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 198 preliminary ? 2011-2012 microchip technology inc. register 20-3: rtctime: rtc time value register (1) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x hr10<3:0> hr01<3:0> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x min10<3:0> min01<3:0> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sec10<3:0> sec01<3:0> 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-28 hr10<3:0>: binary-coded decimal value of hours bits, 10 digits; contains a value from 0 to 2 bit 27-24 hr01<3:0>: binary-coded decimal value of hours bits, 1 digit; contains a value from 0 to 9 bit 23-20 min10<3:0>: binary-coded decimal value of minutes bits, 10 digits; contains a value from 0 to 5 bit 19-16 min01<3:0>: binary-coded decimal value of minutes bits, 1 digit; contains a value from 0 to 9 bit 15-12 sec10<3:0>: binary-coded decimal value of seconds bits, 10 digits; contains a value from 0 to 5 bit 11-8 sec01<3:0>: binary-coded decimal value of seconds bits, 1 digit; contains a value from 0 to 9 bit 7-0 unimplemented: read as ? 0 ? note 1: this register is only writable when rtcwren = 1 (rtccon<3>). www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 199 pic32mx1xx/2xx register 20-4: rtcdate: rtc date value register (1) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x year10<3:0> year01<3:0> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x month10<3:0> month01<3:0> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x day10<3:0> day01<3:0> 7:0 u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x ? ? ? ?wday01<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-28 year10<3:0>: binary-coded decimal value of years bits, 10 digits bit 27-24 year01<3:0>: binary-coded decimal value of years bits, 1 digit bit 23-20 month10<3:0>: binary-coded decimal value of months bits, 10 digits; contains a value from 0 to 1 bit 19-16 month01<3:0>: binary-coded decimal value of months bits, 1 digit; contains a value from 0 to 9 bit 15-12 day10<3:0>: binary-coded decimal value of days bits, 10 digits; contains a value from 0 to 3 bit 11-8 day01<3:0>: binary-coded decimal value of days bits, 1 digit; contains a value from 0 to 9 bit 7-4 unimplemented: read as ? 0 ? bit 3-0 wday01<3:0>: binary-coded decimal value of weekdays bits,1 digit; contains a value from 0 to 6 note 1: this register is only writable when rtcwren = 1 (rtccon<3>). www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 200 preliminary ? 2011-2012 microchip technology inc. register 20-5: alrmtime: alarm time value register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x hr10<3:0> hr01<3:0> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x min10<3:0> min01<3:0> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sec10<3:0> sec01<3:0> 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-28 hr10<3:0>: binary coded decimal value of hours bits, 10 digits; contains a value from 0 to 2 bit 27-24 hr01<3:0>: binary coded decimal value of hours bits, 1 digit; contains a value from 0 to 9 bit 23-20 min10<3:0>: binary coded decimal value of minutes bits, 10 digits; contains a value from 0 to 5 bit 19-16 min01<3:0>: binary coded decimal value of minutes bits, 1 digit; contains a value from 0 to 9 bit 15-12 sec10<3:0>: binary coded decimal value of seconds bits, 10 digits; contains a value from 0 to 5 bit 11-8 sec01<3:0>: binary coded decimal value of seconds bits, 1 digit; contains a value from 0 to 9 bit 7-0 unimplemented: read as ? 0 ? www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 201 pic32mx1xx/2xx register 20-6: alrmdate: alarm date value register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x month10<3:0> month01<3:0> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x day10<1:0> day01<3:0> 7:0 u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x ? ? ? ? wday01<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-24 unimplemented: read as ? 0 ? bit 23-20 month10<3:0>: binary coded decimal value of months bits, 10 digits; contains a value from 0 to 1 bit 19-16 month01<3:0>: binary coded decimal value of months bits , 1 digit; contains a value from 0 to 9 bit 15-12 day10<3:0>: binary coded decimal value of days bits, 10 digits; contains a value from 0 to 3 bit 11-8 day01<3:0>: binary coded decimal value of days bits, 1 digit; contains a value from 0 to 9 bit 7-4 unimplemented: read as ? 0 ? bit 3-0 wday01<3:0>: binary coded decimal value of weekdays bits, 1 digit; contains a value from 0 to 6 www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 202 preliminary ? 2011-2012 microchip technology inc. notes: www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 203 pic32mx1xx/2xx 21.0 10-bit analog-to-digital converter (adc) the pic32mx1xx/2xx 10-bit analog-to-digital converter (adc) includes the following features: ? successive approximation register (sar) conversion ? up to 1 msps conversion speed ? up to 13 analog input pins ? external voltage reference input pins ? one unipolar, differential sample and hold amplifier (sha) ? automatic channel scan mode ? selectable conversion trigger source ? 16-word conversion result buffer ? selectable buffer fill modes ? eight conversion result format options ? operation during cpu sleep and idle modes a block diagram of the 10-bit adc is illustrated in figure 21-1 . the 10-bit adc has up to 13 analog input pins, designated an0-an12. in addition, there are two analog input pins for external voltage reference connections. these voltage reference inputs may be shared with other analog input pins and may be common to other analog module references. figure 21-1: adc1 module block diagram note 1: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 17. ?10-bit analog-to-digital converter (adc)? (ds61104) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. sar adc s&h adc1buf0 adc1buf1 adc1buf2 adc1buff adc1bufe ctmut (3) iv ref (4) an1 v refl ch0sb<4:0> ch0na ch0nb + - ch0sa<4:0> channel scan cscna alternate v ref + (1) av dd av ss v ref - (1) note 1: v ref + and v ref - inputs can be multiplexed with other analog inputs. 2: an8 is only available on 44- pin devices. an6 and an7 are no t available on 28-pin devices. 3: connected to the ctmu module. see section 24.0 ?charge time measurement unit (ctmu)? for more information. 4: see section 23.0 ?comparator voltage reference (cv ref )? for more information. 5: this selection is only used with ct mu capacitive and time measurement. input selection v refh v refl vcfg<2:0> an12 (2) an0 open (5) ctmui (3) www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 204 preliminary ? 2011-2012 microchip technology inc. figure 21-2: adc conversion clock period block diagram 1 0 div 2 t pb (2) adc conversion clock multiplier 2, 4,..., 512 adrc t ad 8 adcs<7:0> frc (1) note 1: see section 29.0 ?electrical characteristics? for the exact frc clock value. 2: refer to figure 8-1 in section 8.0 ?oscillator configuration? for more information. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 205 pic32mx1xx/2xx register 21-1: ad1con1: adc control register 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 on (1) ?sidl ? ? form<2:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0, hsc r/c-0, hsc ssrc<2:0> clrasam ? asam samp (2) done (3) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: adc operating mode bit (1) 1 = adc module is operating 0 = adc module is not operating bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-11 unimplemented: read as ? 0 ? bit 10-8 form<2:0>: data output format bits 011 = signed fractional 16-bit (dout = 0000 0000 0000 0000 sddd dddd dd00 0000 ) 010 = fractional 16-bit (dout = 0000 0000 0000 0000 dddd dddd dd00 0000 ) 001 = signed integer 16-bit (dout = 0000 0000 0000 0000 ssss sssd dddd dddd ) 000 = integer 16-bit (dout = 0000 0000 0000 0000 0000 00dd dddd dddd ) 111 = signed fractional 32-bit (dout = sddd dddd dd00 0000 0000 0000 0000 ) 110 = fractional 32-bit (dout = dddd dddd dd00 0000 0000 0000 0000 0000 ) 101 = signed integer 32-bit (dout = ssss ssss ssss ssss ssss sssd dddd dddd ) 100 = integer 32-bit (dout = 0000 0000 0000 0000 0000 00dd dddd dddd ) bit 7-5 ssrc<2:0>: conversion trigger source select bits 111 = internal counter ends sampling and starts conversion (auto convert) 110 = reserved 101 = reserved 100 = reserved 011 = ctmu ends sampling and starts conversion 010 = timer 3 period match ends sampling and starts conversion 001 = active transition on int0 pin ends sampling and starts conversion 000 = clearing samp bit ends sampling and starts conversion note 1: when using 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 2: if asam = 0 , software can write a ? 1 ? to start sampling. this bit is automatically set by hardware if asam = 1 . if ssrc = 0 , software can write a ?0? to end sampling and start conversion. if ssrc ? 0 ?, this bit is automatically cleared by hardware to end sampling and start conversion. 3: this bit is automatically set by hardware when analog-to-digital conversion is complete. software can write a ? 0 ? to clear this bit (a write of ? 1 ? is not allowed). clearing this bit does not affect any operation already in progress. this bit is automatically clea red by hardware at the start of a new conversion. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 206 preliminary ? 2011-2012 microchip technology inc. bit 4 clrasam: stop conversion sequence bit (when the first adc interrupt is generated) 1 = stop conversions when the first adc interrupt is generated. hardwa re clears the asam bit when the adc interrupt is generated. 0 = normal operation, buffer contents will be overwritten by the next conversion sequence bit 3 unimplemented: read as ? 0 ? bit 2 asam: adc sample auto-start bit 1 = sampling begins immediately after last conver sion completes; samp bi t is automatically set. 0 = sampling begins when samp bit is set bit 1 samp: adc sample enable bit (2) 1 = the adc sample and hold amplifier is sampling 0 = the adc sample/hold amplifier is holding when asam = 0 , writing ? 1 ? to this bit starts sampling. when ssrc = 000 , writing ? 0 ? to this bit will end sampling and start conversion. bit 0 done: analog-to-digital conversion status bit (3) 1 = analog-to-digital conversion is done 0 = analog-to-digital conversion is not done or has not started clearing this bit will not affect any operation in progress. register 21-1: ad1con1: adc cont rol register 1 (continued) note 1: when using 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 2: if asam = 0 , software can write a ? 1 ? to start sampling. this bit is automatically set by hardware if asam = 1 . if ssrc = 0 , software can write a ?0? to end sampling and start conversion. if ssrc ? 0 ?, this bit is automatically cleared by hardware to end sampling and start conversion. 3: this bit is automatically set by hardware when analog-to-digital conversion is complete. software can write a ? 0 ? to clear this bit (a write of ? 1 ? is not allowed). clearing this bit does not affect any operation already in progress. this bit is automatically clear ed by hardware at the start of a new conversion. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 207 pic32mx1xx/2xx register 21-2: ad1con2: adc control register 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 u-0 vcfg<2:0> offcal ?cscna ? ? 7:0 r-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bufs ? smpi<3:0> bufm alts legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-13 vcfg<2:0>: voltage reference configuration bits v refh v refl 000 av dd avss 001 external v ref + pin av ss 010 av dd external v ref - pin 011 external v ref + pin external v ref - pin 1xx av dd av ss bit 12 offcal: input offset calibration mode select bit 1 = enable offset calibration mode positive and negative inputs of the sample and hold amplifier are connected to v refl 0 = disable offset calibration mode the inputs to the sample and hold amplifier are controlled by ad1chs or ad1cssl bit 11 unimplemented: read as ? 0 ? bit 10 cscna: input scan select bit 1 = scan inputs 0 = do not scan inputs bit 9-8 unimplemented: read as ? 0 ? bit 7 bufs: buffer fill status bit only valid when bufm = 1 . 1 = adc is currently filling buffer 0x8-0xf, user should access data in 0x0-0x7 0 = adc is currently filling buffer 0x0-0x7, user should access data in 0x8-0xf bit 6 unimplemented: read as ? 0 ? bit 5-2 smpi<3:0>: sample/convert sequences per interrupt selection bits 1111 = interrupts at the completion of conversion for each 16 th sample/convert sequence 1110 = interrupts at the completion of conversion for each 15 th sample/convert sequence ? ? ? 0001 = interrupts at the completion of conversion for each 2 nd sample/convert sequence 0000 = interrupts at the completion of conv ersion for each sample/convert sequence bit 1 bufm: adc result buffer mode select bit 1 = buffer configured as two 8-word buffers, adc1buf7-adc1buf0, adc1buff-adcbuf8 0 = buffer configured as one 16-word buffer adc1buff-adc1buf0 bit 0 alts: alternate input sample mode select bit 1 = uses sample a input multiplexer settings for first sample, then alternates between sample b and sample a input multiplexer settings for all subsequent samples 0 = always use sample a input multiplexer settings www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 208 preliminary ? 2011-2012 microchip technology inc. register 21-3: ad1con3: adc control register 3 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adrc ? ? samc<4:0> (1) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w r/w-0 adcs<7:0> (2) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 adrc: adc conversion clock source bit 1 = clock derived from frc 0 = clock derived from peripheral bus clock (pbclk) bit 14-13 unimplemented: read as ? 0 ? bit 12-8 samc<4:0>: auto-sample time bits (1) 11111 =31 t ad ? ? ? 00001 = 1 t ad 00000 = 0 t ad (not allowed) bit 7-0 adcs<7:0>: adc conversion clock select bits (2) 11111111 =t pb ? 2 ? (adcs<7:0> + 1) = 512 ? t pb = t ad ? ? ? 00000001 =t pb ? 2 ? (adcs<7:0> + 1) = 4 ? t pb = t ad 00000000 =t pb ? 2 ? (adcs<7:0> + 1) = 2 ? t pb = t ad note 1: this bit is only used if the ss rc<2:0> bits (ad1con1<7:5>) = 111 . 2: this bit is not used if the adrc bit (ad1con3<15>) = 1 . www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 209 pic32mx1xx/2xx register 21-4: ad1chs: adc input select register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ch0nb ? ? ? ch0sb<3:0> 23:16 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ch0na ? ? ? ch0sa<3:0> 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 ch0nb: negative input select bit for sample b 1 = channel 0 negative input is an1 0 = channel 0 negative input is v refl bit 30-28 unimplemented: read as ? 0 ? bit 27-24 ch0sb<3:0>: positive input select bits for sample b 1111 = channel 0 positive input is open (1) 1110 = channel 0 positive input is iv ref (2) 1101 = channel 0 positive input is ctmu temperature sensor (ctmut) (3) 1100 = channel 0 positive input is an12 (4) ? ? ? 0001 = channel 0 positive input is an1 0000 = channel 0 positive input is an0 bit 23 ch0na: negative input select bit fo r sample a multiplexer setting (2) 1 = channel 0 negative input is an1 0 = channel 0 negative input is v refl bit 22-20 unimplemented: read as ? 0 ? bit 19-16 ch0sa<3:0>: positive input select bits fo r sample a multiplexer setting 1111 = channel 0 positive input is open (1) 1110 = channel 0 positive input is iv ref (2) 1101 = channel 0 positive input is ctmu temperature (ctmut) (3) 1100 = channel 0 positive input is an12 (4) ? ? ? 0001 = channel 0 positive input is an1 0000 = channel 0 positive input is an0 bit 15-0 unimplemented: read as ? 0 ? note 1: this selection is only used with ct mu capacitive and time measurement. 2: see section 23.0 ?comparator voltage reference (cv ref )? for more information. 3: see section 24.0 ?charge time measurement unit (ctmu)? for more information. 4: an12 is only available on 44-pin devices. an6-an8 are not available on 28-pin devices. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 210 preliminary ? 2011-2012 microchip technology inc. register 21-5: ad1cssl: adc input scan select register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cssl15 cssl14 cssl13 cssl12 cssl11 cssl10 cssl9 cssl8 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cssl7 cssl6 cssl5 cssl4 cssl3 cssl2 cssl1 cssl0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 cssl<15:0>: adc input pin scan selection bits (1,2) 1 = select anx for input scan 0 = skip anx for input scan note 1: cssl = anx, where x = 0-12; cssl13 select s ctmu input for scan; cssl14 selects iv ref for scan; cssl15 selects v ss for scan. 2: on devices with less than 13 analog inputs, all csslx bits can be selected; however, inputs selected for scan without a corresponding input on the device will convert to v refl . www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 211 pic32mx1xx/2xx 22.0 comparator the pic32mx1xx/2xx analog comparator module contains three comparators that can be configured in a variety of ways. following are some of the key features of this module: ? selectable inputs available include: - analog inputs multiplexed with i/o pins - on-chip internal absolute voltage reference (iv ref ) - comparator voltage reference (cv ref ) ? outputs can be inverted ? selectable interrupt generation a block diagram of the comp arator module is provided in figure 22-1 . figure 22-1: comparator block diagram note 1: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 19. ?comparator? (ds61110) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. c3ind c3ina c3out cmp3 coe cref cch<1:0> cpol c3inc c3inb cv ref (1) iv ref (1.2v) c2ind c2ina c2out cmp2 coe cref cch<1:0> cpol c2inc c2inb c1ind c1ina c1out cmp1 coe cref cch<1:0> cpol c1inc c1inb cmstat cm1con cmstat cm2con cmstat cm3con to ctmu module (pulse generator) note 1: internally connected. see section 23.0 ?comparator voltage reference (cv ref )? for more information. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 212 preliminary ? 2011-2012 microchip technology inc. register 22-1: cmxcon: co mparator control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 r-0 on (1) coe cpol (2) ? ? ? ?cout 7:0 r/w-1 r/w-1 u-0 r/w-0 u-0 u-0 r/w-1 r/w-1 evpol<1:0> ? cref ? ? cch<1:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: comparator on bit (1) 1 = module is enabled. setting this bit does not affect the other bits in this register 0 = module is disabled and does not consume current. clearing this bit does not affect the other bits in this register bit 14 coe: comparator output enable bit 1 = comparator output is driven on the output cxout pin 0 = comparator output is not driven on the output cxout pin bit 13 cpol: comparator output inversion bit (2) 1 = output is inverted 0 = output is not inverted bit 12-9 unimplemented: read as ? 0 ? bit 8 cout: comparator output bit 1 = output of the comparator is a ? 1 ? 0 = output of the comparator is a ? 0 ? bit 7-6 evpol<1:0>: interrupt event polarity select bits 11 = comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output 10 = comparator interrupt is generated on a high-to-low transition of the comparator output 01 = comparator interrupt is generated on a low-to-high transition of the comparator output 00 = comparator interrupt generation is disabled bit 5 unimplemented: read as ? 0 ? bit 4 cref: comparator positive input configure bit 1 = comparator non-inverting input is connected to the internal cv ref 0 = comparator non-inverting input is connected to the c x ina pin bit 3-2 unimplemented: read as ? 0 ? bit 1-0 cch<1:0>: comparator negative input select bits for comparator 11 = comparator inverting input is connected to the iv ref 10 = comparator inverting input is connected to the cxind pin 01 = comparator inverting input is connected to the cxinc pin 00 = comparator inverting input is connected to the cxinb pin note 1: when using the 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 2: setting this bit will invert the signal to the comparator interrupt generator as well. this will result in an interrupt being generated on the opposite edge from the one se lected by evpol<1:0>. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 213 pic32mx1xx/2xx register 22-2: cmstat: comparator status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ? ?sidl ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 u-0 r-0 r-0 r-0 ? ? ? ? ? c3out c2out c1out legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle control bit 1 = all comparator modules are disabled in idle mode 0 = all comparator modules continue to operate in the idle mode bit 12-3 unimplemented: read as ? 0 ? bit 2 c3out: comparator output bit 1 = output of comparator 3 is a ? 1 ? 0 = output of comparator 3 is a ? 0 ? bit 1 c2out: comparator output bit 1 = output of comparator 2 is a ? 1 ? 0 = output of comparator 2 is a ? 0 ? bit 0 c1out: comparator output bit 1 = output of comparator 1 is a ? 1 ? 0 = output of comparator 1 is a ? 0 ? www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 214 preliminary ? 2011-2012 microchip technology inc. notes: www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 215 pic32mx1xx/2xx 23.0 comparator voltage reference (cv ref ) the cv ref module is a 16-tap, resistor ladder network that provides a selectable reference voltage. although its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them. a block diagram of the module is illustrated in figure 23-1 . the resistor ladder is segmented to provide two ranges of voltage reference values and has a power-down function to conserve power when the reference is not being used. the module?s supply refer- ence can be provided from either device v dd /v ss or an external voltage reference. the cv ref output is avail- able for the comparators and typically available for pin output. the comparator voltage reference has the following features: ? high and low range selection ? sixteen output levels available for each range ? internally connected to comparators to conserve device pins ? output can be connected to a pin figure 23-1: comparator voltage reference block diagram note 1: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source. to complement the inform ation in this data sheet, refer to section 20. ?comparator voltage reference (cv ref )? (ds61109) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32) . 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. 16-to-1 mux cvr<3:0> 8r r cvren cvrss = 0 av dd v ref + cvrss = 1 8r cvrss = 0 v ref - cvrss = 1 r r r r r r 16 steps cvrr cv refout av ss cvrcon cv ref cv rsrc www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 216 preliminary ? 2011-2012 microchip technology inc. register 23-1: cvrcon: comparator voltage reference control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 on (1) ? ? ? ? ? ? ? 7:0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? cvroe cvrr cvrss cvr<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: comparator voltage reference on bit (1) 1 = module is enabled setting this bit does not affect other bits in the register. 0 = module is disabled and does not consume current. clearing this bit does not affect the other bits in the register. bit 14-7 unimplemented: read as ? 0 ? bit 6 cvroe: cv refout enable bit 1 = voltage level is output on cv refout pin 0 = voltage level is disconnected from cv refout pin bit 5 cvrr: cv ref range selection bit 1 = 0 to 0.67 cv rsrc , with cv rsrc /24 step size 0 = 0.25 cv rsrc to 0.75 cv rsrc , with cv rsrc /32 step size bit 4 cvrss: cv ref source selection bit 1 = comparator voltage reference source, cv rsrc = (v ref +) ? (v ref -) 0 = comparator voltage reference source, cv rsrc = av dd ? av ss bit 3-0 cvr<3:0>: cv ref value selection 0 cvr<3:0> 15 bits when cvrr = 1 : cv ref = (cvr<3:0>/24) ? (cv rsrc ) when cvrr = 0 : cv ref =1/4 ? (cv rsrc ) + (cvr<3:0>/32) ? (cv rsrc ) note 1: when using 1:1 pbclk divisor, the user?s software should not read/write the per ipheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 217 pic32mx1xx/2xx 24.0 charge time measurement unit (ctmu) the charge time measurement unit (ctmu) is a flex- ible analog module that has a configurable current source with a digital configur ation circuit built around it. the ctmu can be used for differential time measure- ment between pulse sources and can be used for gen- erating an asynchronous pulse. by working with other on-chip analog modules, the ctmu can be used for high resolution time measurement, measure capaci- tance, measure relative changes in capacitance or generate output pulses with a specific time delay. the ctmu is ideal for interfacing with capacitive-based sensors. the module includes the following key features: ? up to 13 channels available for capacitive or time measurement input ? on-chip precision current source ? 16-edge input trigger sources ? selection of edge or level-sensitive inputs ? polarity control for each edge source ? control of edge sequence ? control of response to edges ? high precision time measurement ? time delay of external or internal signal asynchro- nous to system clock ? integrated temperature sensing diode ? control of current source during auto-sampling ? four current source ranges ? time measurement resolution of one nanosecond a block diagram of the ctmu is shown in figure 24-1 . figure 24-1: ctmu block diagram note 1: this data sheet summarizes the fea- tures of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 37. ?charge time measurement unit (ctmu)? (ds61167) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. cted1 cted13 current source edge control logic ctmucon1 or ctmucon2 pulse generator ctmui comparator 2 timer1 oc1 current control itrim<5:0> irng<1:0> ctmuicon ctmu control logic edg1stat edg2stat adc ctpls ic1-ic3 cmp1-cmp3 c2inb cdelay ctmut temperature sensor current control selection tgen edg1stat, edg2stat ctmut 0 edg1stat = edg2stat ctmui 0 edg1stat edg2stat ctmup 1 edg1stat edg2stat no connect 1 edg1stat = edg2stat trigger tgen ctmup external capacitor for pulse generation (to adc s&h capacitor) (to adc) pbclk ? ? ? www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 218 preliminary ? 2011-2012 microchip technology inc. register 24-1: ctmucon: ctmu control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 edg1mod edg1pol edg1sel<3:0> edg2stat edg1stat 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 edg2mod edg2pol edg2sel<3:0> ? ? 15:8 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 on ?ctmusidltgen (1) edgen edgseqen idissen (2) cttrig 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 itrim<5:0> irng<1:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 edg1mod: edge1 edge sampling select bit 1 = input is edge-sensitive 0 = input is level-sensitive bit 30 edg1pol: edge 1 polarity select bit 1 = edge1 programmed for a positive edge response 0 = edge1 programmed for a negative edge response bit 29-26 edg1sel<3:0>: edge 1 source select bits 1111 = c3out pin is selected 1110 = c2out pin is selected 1101 = c1out pin is selected 1100 = ic3 capture event is selected 1011 = ic2 capture event is selected 1010 = ic1 capture event is selected 1001 = cted8 pin is selected 1000 = cted7 pin is selected 0111 = cted6 pin is selected 0110 = cted5 pin is selected 0101 = cted4 pin is selected 0100 = cted3 pin is selected 0011 = cted1 pin is selected 0010 = cted2 pin is selected 0001 = oc1 compare event is selected 0000 = timer1 event is selected bit 25 edg2stat: edge2 status bit indicates the status of edge2 and can be written to control edge source 1 = edge2 has occurred 0 = edge2 has not occurred note 1: when this bit is set for pulse delay generation, the edg2sel<2:0> bits must be set to ? 1110 ? to select c2out. 2: the adc module sample and hold capacitor is not automatically discharged between sample/conversion cycles. software using the adc as pa rt of a capacitive measurement, must discharge the adc capacitor before conducting the measurement. the idissen bit, when set to ? 1 ?, performs this function. the adc module must be sampling while the idissen bit is active to connect the discharge sink to the capacitor array. 3: refer to the ctmu current source specifications ( table 29-39 ) in section 29.0 ?electrical characteristics? for current values. 4: this bit setting is not available for the ctmu temperature diode. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 219 pic32mx1xx/2xx bit 24 edg1stat: edge1 status bit indicates the status of edge1 and can be written to control edge source 1 = edge1 has occurred 0 = edge1 has not occurred bit 23 edg2mod: edge2 edge sampling select bit 1 = input is edge-sensitive 0 = input is level-sensitive bit 22 edg2pol: edge 2 polarity select bit 1 = edge2 programmed for a positive edge response 0 = edge2 programmed for a negative edge response bit 21-18 edg2sel<3:0>: edge 2 source select bits 1111 = c3out pin is selected 1110 = c2out pin is selected 1101 = c1out pin is selected 1100 = pbclk clock is selected 1011 = ic3 capture event is selected 1010 = ic2 capture event is selected 1001 = ic1 capture event is selected 1000 = cted13 pin is selected 0111 = cted12 pin is selected 0110 = cted11 pin is selected 0101 = cted10 pin is selected 0100 = cted9 pin is selected 0011 = cted1 pin is selected 0010 = cted2 pin is selected 0001 = oc1 compare event is selected 0000 = timer1 event is selected bit 17-16 unimplemented: read as ? 0 ? bit 15 on: on enable bit 1 = module is enabled 0 = module is disabled bit 14 unimplemented: read as ? 0 ? bit 13 ctmusidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12 tgen: time generation enable bit (1) 1 = enables edge delay generation 0 = disables edge delay generation bit 11 edgen: edge enable bit 1 = edges are not blocked 0 = edges are blocked register 24-1: ctmucon: ctmu control register (continued) note 1: when this bit is set for pulse delay generatio n, the edg2sel<2:0> bits must be set to ? 1110 ? to select c2out. 2: the adc module sample and hold capacitor is not automatically discharged between sample/conversion cycles. software using the adc as pa rt of a capacitive measurement, must discharge the adc capacitor before conducting the measurement . the idissen bit, when set to ? 1 ?, performs this function. the adc module must be sampling while the idissen bit is active to connect the discharge sink to the capacitor array. 3: refer to the ctmu current source specifications ( table 29-39 ) in section 29.0 ?electrical characteristics? for current values. 4: this bit setting is not available for the ctmu temperature diode. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 220 preliminary ? 2011-2012 microchip technology inc. bit 10 edgseqen: edge sequence enable bit 1 = edge1 must occur before edge2 can occur 0 = no edge sequence is needed bit 9 idissen: analog current source control bit (2) 1 = analog current source output is grounded 0 = analog current source output is not grounded bit 8 cttrig: trigger control bit 1 = trigger output is enabled 0 = trigger output is disabled bit 7-2 itrim<5:0>: current source trim bits 011111 = maximum positive change from nominal current 011110 ? ? ? 000001 = minimum positive change from nominal current 000000 = nominal current output specified by irng<1:0> 111111 = minimum negative change from nominal current ? ? ? 100010 100001 = maximum negative change from nominal current bit 1-0 irng<1:0>: current range select bits (3) 11 = 100 times base current 10 = 10 times base current 01 = base current level 00 = 1000 times base current (4) register 24-1: ctmucon: ctmu control register (continued) note 1: when this bit is set for pulse delay generation, the edg2sel<2:0> bits must be set to ? 1110 ? to select c2out. 2: the adc module sample and hold capacitor is not automatically discharged between sample/conversion cycles. software using the adc as pa rt of a capacitive measurement, must discharge the adc capacitor before conducting the measurement. the idissen bit, when set to ? 1 ?, performs this function. the adc module must be sampling while the idissen bit is active to connect the discharge sink to the capacitor array. 3: refer to the ctmu current source specifications ( table 29-39 ) in section 29.0 ?electrical characteristics? for current values. 4: this bit setting is not available for the ctmu temperature diode. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 221 pic32mx1xx/2xx 25.0 power-saving features this section describes power-saving features for the pic32mx1xx/2xx. the pic32 devices offer a total of nine methods and modes, organized into two categories, that allow the user to balance power consumption with device performance. in all of the methods and modes described in this section, power- saving is controlled by software. 25.1 power saving with cpu running when the cpu is running, power consumption can be controlled by reducing t he cpu clock frequency, lowering the pbclk and by individually disabling modules. these methods are grouped into the following categories: ? frc run mode: the cpu is clocked from the frc clock source with or without postscalers. ? lprc run mode: the cpu is clocked from the lprc clock source. ?s osc run mode: the cpu is clocked from the s osc clock source. in addition, the peripheral bus scaling mode is available where peripherals are clocked at the programmable fraction of the cpu clock (sysclk). 25.2 cpu halted methods the device supports two power-saving modes, sleep and idle, both of which halt the clock to the cpu. these modes operate with all clock sources, as listed below: ?p osc idle mode: the system clock is derived from the p osc . the system clock source continues to operate. peripherals continue to operate, but can optionally be individually disabled. ? frc idle mode: the system clock is derived from the frc with or without postscalers. peripherals continue to operate, but can optionally be individually disabled. ?s osc idle mode: the system clock is derived from the s osc . peripherals continue to operate, but can optionally be individually disabled. ? lprc idle mode: the system clock is derived from the lprc. peripherals cont inue to operate, but can optionally be individua lly disabled. this is the lowest power mode for the device with a clock running. ? sleep mode: the cpu, the system clock source and any peripherals that operate from the system clock source are halted. some peripherals can operate in sleep using specific clock sources. this is the lowest power mode for the device. 25.3 power-saving operation peripherals and the cpu can be halted or disabled to further reduce power consumption. 25.3.1 sleep mode sleep mode has the lowest pow er consumption of the device power-saving operating modes. the cpu and most peripherals are halted. select peripherals can continue to operate in sleep mode and can be used to wake the device from sleep. see the individual peripheral module sections for descriptions of behavior in sleep. sleep mode includes the following characteristics: ? the cpu is halted. ? the system clock source is typically shutdown. see section 25.3.3 ?peripheral bus scaling method? for specific information. ? there can be a wake-up delay based on the oscillator selection. ? the fail-safe clock monitor (fscm) does not operate during sleep mode. ? the bor circuit remains operative during sleep mode. ? the wdt, if enabled, is not automatically cleared prior to entering sleep mode. ? some peripherals can cont inue to operate at limited functionality in sleep mode. these peripherals include i/o pins that detect a change in the input signal, wdt, adc, uart and peripherals that use an external clock input or the internal lprc oscillator (e.g., rtcc, timer1 and input capture). ? i/o pins continue to sink or source current in the same manner as they do when the device is not in sleep. ? the usb module can override the disabling of the posc or frc. refer to the usb section for specific details. ? modules can be individually disabled by software prior to entering sleep in order to further reduce consumption. note 1: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 10. ?power- saving features? (ds61130) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 222 preliminary ? 2011-2012 microchip technology inc. the processor will exit, or ?wake-up?, from sleep on one of the following events: ? on any interrupt from an enabled source that is operating in sleep. the interrupt priority must be greater than the current cpu priority. ? on any form of device reset. ? on a wdt time-out. if the interrupt priority is lower than or equal to the current priority, the cpu will remain halted, but the pbclk will start running and the device will enter into idle mode. 25.3.2 idle mode in idle mode, the cpu is halted but the system clock (sysclk) source is still enabled. this allows peripher- als to continue operation when the cpu is halted. peripherals can be individually configured to halt when entering idle by setting their respective sidl bit. latency, when exiting idle mode, is very low due to the cpu oscillator source remaining active. the device enters idle mode when the slpen bit (osccon<4>) is clear and a wait instruction is executed. the processor will wake or exit from idle mode on the following events: ? on any interrupt event for which the interrupt source is enabled. the priority of the interrupt event must be greater than the current priority of the cpu. if the priority of the interrupt event is lower than or equal to curre nt priority of the cpu, the cpu will remain halted and the device will remain in idle mode. ? on any form of device reset ? on a wdt time-out interrupt 25.3.3 peripheral bus scaling method most of the peripherals on the device are clocked using the pbclk. the peripheral bus can be scaled relative to the sysclk to minimize the dynamic power consumed by the peripherals. the pbcl k divisor is controlled by pbdiv<1:0> (osccon<20:19>), allowing sysclk to pbclk ratios of 1:1, 1:2, 1:4 and 1:8. all peripherals using pbclk are affected when the divisor is changed. peripherals such as the usb, interrupt controller, dma, and the bus matrix are cloc ked directly from sysclk. as a result, they are not affected by pbclk divisor changes. changing the pbclk divisor affects: ? the cpu to peripheral access latency. the cpu has to wait for next pbclk edge for a read to complete. in 1:8 mode, this results in a latency of one to seven sysclks. ? the power consumption of the peripherals. power consumption is directly proportional to the fre- quency at which the peripherals are clocked. the greater the divisor, the lower the power consumed by the peripherals. to minimize dynamic power, the pb divisor should be chosen to run the peripherals at the lowest frequency that provides acceptabl e system performance. when selecting a pbclk divider, peripheral clock require- ments, such as baud rate accuracy, should be taken into account. for example, the uart peripheral may not be able to achieve all baud rate values at some pbclk divider depending on the sysclk value. note 1: changing the pbclk divider ratio requires recalculation of peripheral tim- ing. for example, assume the uart is configured for 9600 baud with a pb clock ratio of 1:1 and a p osc of 8 mhz. when the pb clock divisor of 1:2 is used, the input frequency to the baud clock is cut in half; therefore, the baud rate is reduced to 1/2 its former value. due to numeric truncation in calculations (such as the baud rate divisor), the actual baud rate may be a tiny percentage different than expected. for this reason, any timing cal- culation required for a peripheral should be performed with the new pb clock fre- quency instead of scaling the previous value based on a change in the pb divisor ratio. 2: oscillator start-up and pll lock delays are applied when switching to a clock source that was disabled and that uses a crystal and/or the pll. for example, assume the clock source is switched from p osc to lprc just prior to entering sleep in order to save power. no oscillator start- up delay would be applied when exiting idle. however, when switching back to p osc , the appropriate pll and/or oscillator start-up/lock delays would be applied. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 223 pic32mx1xx/2xx 25.4 peripheral module disable the peripheral module disable (pmd) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. when a peripheral is disabl ed using the appropriate pmd control bit, the peripheral is in a minimum power consumption state. the control and status registers associated with the peripheral are also disabled, so writes to those registers do not have effect and read values are invalid. to disable a peripheral, the associated pmdx bit must be set to ? 1 ?. to enable a peripheral, the associated pmdx bit must be cleared (default). see table 25-1 for more information. table 25-1: peripheral module disable bits and locations (1) note: disabling a peripheral module while it?s on bit is set, may result in undefined behavior. the on bit for the associated peripheral module must be cleared prior to disable a module via the pmdx bits. peripheral pmdx bit name register name and bit location adc1 ad1md pmd1<0> ctmu ctmumd pmd1<8> comparator voltage reference cvrmd pmd1<12> comparator 1 cmp1md pmd2<0> comparator 2 cmp2md pmd2<1> comparator 3 cmp3md pmd2<2> input capture 1 ic1md pmd3<0> input capture 2 ic2md pmd3<1> input capture 3 ic3md pmd3<2> input capture 4 ic4md pmd3<3> input capture 5 ic5md pmd3<4> output compare 1 oc1md pmd3<16> output compare 2 oc2md pmd3<17> output compare 3 oc3md pmd3<18> output compare 4 oc4md pmd3<19> output compare 5 oc5md pmd3<20> timer1 t1md pmd4<0> timer2 t2md pmd4<1> timer3 t3md pmd4<2> timer4 t4md pmd4<3> timer5 t5md pmd4<4> uart1 u1md pmd5<0> uart2 u2md pmd5<1> spi1 spi1md pmd5<8> spi2 spi2md pmd5<9> i2c1 i2c1md pmd5<16> i2c2 i2c2md pmd5<17> usb (2) usbmd pmd5<24> rtcc rtccmd pmd6<0> reference clock ou tput refomd pmd6<1> pmp pmpmd pmd6<16> note 1: not all modules and associated pmdx bits are available on all devices. see table 1: ?pic32mx1xx general purpose fa mily features? and table 2: ?pic32mx2xx usb family features? for the lists of available peripherals. 2: module must not be busy after clearing the associ ated on bit and prior to setting the usbmd bit. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 224 preliminary ? 2011-2012 microchip technology inc. 25.4.1 controllin g configuration changes because peripherals can be disabled during run time, some restrictions on disabling peripherals are needed to prevent accidental configuration changes. pic32 devices include two features to prevent alterations to enabled or disabled peripherals: ? control register lock sequence ? configuration bit select lock 25.4.1.1 control register lock under normal operation, writes to the pmdx registers are not allowed. attempted writes appear to execute normally, but the contents of the registers remain unchanged. to change these registers, they must be unlocked in hardware. the register lock is controlled by the pmdlock configuration bit (cfgcon<12>). set- ting pmdlock prevents writes to the control registers; clearing pmdlock allows writes. to set or clear pmdlock, an unlock sequence must be executed. refer to section 6. ?oscillator? (ds61112) in the ?pic32 family reference manual? for details. 25.4.1.2 configuratio n bit select lock as an additional level of safety, the device can be configured to prevent more than one write session to the pmdx registers. the pm dl1way configuration bit (devcfg3<28>) blocks the pmdlock bit from being cleared after it has been set once. if pmdlock remains set, the register unlock procedure does not execute, and the peripheral pin select control registers cannot be written to. the only way to clear the bit and re-enable pmd functionality is to perform a device reset. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 225 pic32mx1xx/2xx 26.0 special features pic32mx1xx/2xx devices include several features intended to maximize application flexibility and reliabil- ity and minimize cost through elimination of external components. these are: ? flexible device configuration ? watchdog timer (wdt) ? joint test action group (jtag) interface ? in-circuit serial programming? (icsp?) 26.1 configuration bits the configuration bits can be programmed using the following registers to select various device configurations. ? devcfg0: device configuration word 0 ? devcfg1: device configuration word 1 ? devcfg2: device configuration word 2 ? devcfg3: device configuration word 3 ? cfgcon: configuration control register in addition, the devid register ( register 26-6 ) provides device and revision information. note: this data sheet summ arizes the features of the pic32mx1xx/2xx family of devices. however, it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 9. ?watchdog timer and power-up timer? (ds61114), section 32. ?configuration? (ds61124) and section 33. ?programming and diagnostics? (ds61129) in the ?pic32 family reference manual? (ds61132), which is available from the microchip web site ( www.microchip.com/pic32 ). www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 226 preliminary ? 2011-2012 microchip technology inc. register 26-1: devcfg0: d evice configuration word 0 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-1 r-1 r/p r-1 r-1 r-1 r/p ? ? ?cp ? ? ?bwp 23:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 ? ? ? ? ? ? ? ? 15:8 r/p r/p r/p r/p r/p r/p r-1 r-1 pwp<5:0> ? ? 7:0 r-1 r-1 r-1 r/p r/p r/p r/p r/p ? ? ? icesel<1:0> (2) jtagen (1) debug<1:0> legend: r = reserved bit p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 reserved: write ? 0 ? bit 30-29 reserved: write ? 1 ? bit 28 cp: code-protect bit prevents boot and program flash memory from being read or modified by an external pro- gramming device. 1 = protection is disabled 0 = protection is enabled bit 27-25 reserved: write ? 1 ? bit 24 bwp: boot flash write-protect bit prevents boot flash memory from bei ng modified during code execution. 1 = boot flash is writable 0 = boot flash is not writable bit 23-16 reserved: write ? 1 ? note 1: this bit sets the value for the jt agen bit in the cfgcon register. 2: the pgec4/pged4 pin pair is not available on all devices. refer to the ?pin diagrams? section for availability. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 227 pic32mx1xx/2xx bit 15-10 pwp<5:0>: program flash write-protect bits prevents selected program flash memory pa ges from being modified during code execution. 111111 = disabled 111110 = memory below 0x0400 address is write-protected 111101 = memory below 0x0800 address is write-protected 111100 = memory below 0x0c00 address is write-protected 111011 = memory below 0x1000 address is write-protected 111010 = memory below 0x1400 address is write-protected 111001 = memory below 0x1800 address is write-protected 111000 = memory below 0x1c00 address is write-protected 110111 = memory below 0x2000 address is write-protected 110110 = memory below 0x2400 address is write-protected 110101 = memory below 0x2800 address is write-protected 110100 = memory below 0x2c00 address is write-protected 110011 = memory below 0x3000 address is write-protected 110010 = memory below 0x3400 address is write-protected 110001 = memory below 0x3800 address is write-protected 110000 = memory below 0x3c00 address is write-protected 101111 = memory below 0x4000 address is write-protected 101110 = memory below 0x4400 address is write-protected 101101 = memory below 0x4800 address is write-protected 101100 = memory below 0x4c00 address is write-protected 101011 = memory below 0x5000 address is write-protected 101010 = memory below 0x5400 address is write-protected 101001 = memory below 0x5800 address is write-protected 101000 = memory below 0x5c00 address is write-protected 100111 = memory below 0x6000 address is write-protected 100110 = memory below 0x6400 address is write-protected 100101 = memory below 0x6800 address is write-protected 100100 = memory below 0x6c00 address is write-protected 100011 = memory below 0x7000 address is write-protected 100010 = memory below 0x7400 address is write-protected 100001 = memory below 0x7800 address is write-protected 100000 = memory below 0x7c00 address is write-protected 011111 = memory below 0x8000 address is write-protected bit 9-5 reserved: write ? 1 ? bit 4-3 icesel<1:0>: in-circuit emulator/debugger communication channel select bits 11 = pgec1/pged1 pair is used 10 = pgec2/pged2 pair is used 01 = pgec3/pged3 pair is used 00 = pgec4/pged4 pair is used (2) bit 2 jtagen: jtag enable bit (1) 1 = jtag is enabled 0 = jtag is disabled bit 1-0 debug<1:0>: background debugger enable bits (forced to ? 11 ? if code-protect is enabled) 1x = debugger is disabled 0x = debugger is enabled register 26-1: devcfg0: device configuration word 0 (continued) note 1: this bit sets the value for the jt agen bit in the cfgcon register. 2: the pgec4/pged4 pin pair is not available on all devices. refer to the ?pin diagrams? section for availability. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 228 preliminary ? 2011-2012 microchip technology inc. register 26-2: devcfg1: d evice configuration word 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-1 r-1 r-1 r-1 r-1 r-1 r/p r/p ? ? ? ? ? ? fwdtwinsz<1:0> 23:16 r/p r/p r-1 r/p r/p r/p r/p r/p fwdten windis ? wdtps<4:0> 15:8 r/p r/p r/p r/p r-1 r/p r/p r/p fcksm<1:0> fpbdiv<1:0> ? osciofnc poscmod<1:0> 7:0 r/p r-1 r/p r-1 r-1 r/p r/p r/p ieso ? fsoscen ? ?fnosc<2:0> legend: r = reserved bit p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-26 reserved: write ? 1 ? bit 25-24 fwdtwinsz: watchdog timer window size bits 11 = window size is 25% 10 = window size is 37.5% 01 = window size is 50% 00 = window size is 75% bit 23 fwdten: watchdog timer enable bit 1 = watchdog timer is enabled and cannot be disabled by software 0 = watchdog timer is not enabled; it can be enabled in software bit 22 windis: watchdog timer window enable bit 1 = watchdog timer is in non-window mode 0 = watchdog timer is in window mode bit 21 reserved: write ? 1 ? bit 20-16 wdtps<4:0>: watchdog timer postscale select bits 10100 = 1:1048576 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32768 01110 = 1:16384 01101 = 1:8192 01100 = 1:4096 01011 = 1:2048 01010 = 1:1024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 all other combinations not shown result in operation = 10100 note 1: do not disable the p osc (poscmod = 11 ) when using this oscillator source. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 229 pic32mx1xx/2xx bit 15-14 fcksm<1:0>: clock switching and monitor selection configuration bits 1x = clock switching is disabled, fail-safe clock monitor is disabled 01 = clock switching is enabled, fail-safe clock monitor is disabled 00 = clock switching is enabled, fail-safe clock monitor is enabled bit 13-12 fpbdiv<1:0>: peripheral bus clock divisor default value bits 11 = pbclk is sysclk divided by 8 10 = pbclk is sysclk divided by 4 01 = pbclk is sysclk divided by 2 00 = pbclk is sysclk divided by 1 bit 11 reserved: write ? 1 ? bit 10 osciofnc: clko enable configuration bit 1 = clko output disabled 0 = clko output signal active on the osco pin; primar y oscillator must be disabled or configured for the external clock mode (ec) for the clko to be active (poscmod<1:0> = 11 or 00 ) bit 9-8 poscmod<1:0>: primary oscillator configuration bits 11 = primary oscillator disabled 10 = hs oscillator mode selected 01 = xt oscillator mode selected 00 = external clock mode selected bit 7 ieso: internal external switchover bit 1 = internal external switchover mode is enabled (two-speed start-up is enabled) 0 = internal external switchover mode is disabled (two-speed start-up is disabled) bit 6 reserved: write ? 1 ? bit 5 fsoscen: secondary oscillator enable bit 1 = enable secondary oscillator 0 = disable secondary oscillator bit 4-3 reserved: write ? 1 ? bit 2-0 fnosc<2:0>: oscillator selection bits 111 = fast rc oscillator with divide-by-n (frcdiv) 110 = frcdiv16 fast rc oscillator with fixed divide-by-16 postscaler 101 = low-power rc oscillator (lprc) 100 = secondary oscillator (s osc ) 011 = primary oscillator (p osc ) with pll module (xt+pll, hs+pll, ec+pll) 010 = primary oscillator (xt, hs, ec) (1) 001 = fast rc oscillator with divi de-by-n with pll module (frcdiv+pll) 000 = fast rc oscillator (frc) register 26-2: devcfg1: device configuration word 1 (continued) note 1: do not disable the p osc (poscmod = 11 ) when using this oscillator source. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 230 preliminary ? 2011-2012 microchip technology inc. register 26-3: devcfg2: d evice configuration word 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 ? ? ? ? ? ? ? ? 23:16 r-1 r-1 r-1 r-1 r-1 r/p r/p r/p ? ? ? ? ? fpllodiv<2:0> 15:8 r/p r-1 r-1 r-1 r-1 r/p r/p r/p upllen (1) ? ? ? ? upllidiv<2:0> (1) 7:0 r-1 r/p-1 r/p r/p-1 r-1 r/p r/p r/p ? fpllmul<2:0> ? fpllidiv<2:0> legend: r = reserved bit p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-19 reserved: write ? 1 ? bit 18-16 fpllodiv<2:0>: default pll output divisor bits 111 = pll output divided by 256 110 = pll output divided by 64 101 = pll output divided by 32 100 = pll output divided by 16 011 = pll output divided by 8 010 = pll output divided by 4 001 = pll output divided by 2 000 = pll output divided by 1 bit 15 upllen: usb pll enable bit (1) 1 = disable and bypass usb pll 0 = enable usb pll bit 14-11 reserved: write ? 1 ? bit 10-8 upllidiv<2:0>: usb pll input divider bits (1) 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider bit 7 reserved: write ? 1 ? bit 6-4 fpllmul<2:0>: pll multiplier bits 111 = 24x multiplier 110 = 21x multiplier 101 = 20x multiplier 100 = 19x multiplier 011 = 18x multiplier 010 = 17x multiplier 001 = 16x multiplier 000 = 15x multiplier bit 3 reserved: write ? 1 ? note 1: this bit is available on pic32mx2xx devices only. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 231 pic32mx1xx/2xx bit 2-0 fpllidiv<2:0>: pll input divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider register 26-3: devcfg2: device configuration word 2 (continued) note 1: this bit is available on pic32mx2xx devices only. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 232 preliminary ? 2011-2012 microchip technology inc. register 26-4: devcfg3: d evice configuration word 3 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/p r/p r/p r/p r-1 r-1 r-1 r-1 fvbusonio fusbidio iol1way pmdl1way ? ? ? ? 23:16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 ? ? ? ? ? ? ? ? 15:8 r/p r/p r/p r/p r/p r/p r/p r/p userid<15:8> 7:0 r/p r/p r/p r/p r/p r/p r/p r/p userid<7:0> legend: r = reserved bit p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 fvbusonio: usb vbus_on selection bit 1 = v buson pin is controlled by the usb module 0 = v buson pin is controlled by the port function bit 30 fusbidio: usb usbid selection bit 1 = usbid pin is controlled by the usb module 0 = usbid pin is controlled by the port function bit 29 iol1way: peripheral pin select configuration bit 1 = allow only one reconfiguration 0 = allow multiple reconfigurations bit 28 pmdl1way: peripheral module disable configuration bit 1 = allow only one reconfiguration 0 = allow multiple reconfigurations bit 27-16 reserved: write ? 1 ? bit 15-0 userid<15:0>: this is a 16-bit value that is user-defined and is readable via icsp? and jtag www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 233 pic32mx1xx/2xx register 26-5: cfgcon: configuration control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? ?iolock (1) pmdlock (1) ? ? ? ? 7:0 u-0 u-0 u-0 u-0 r/w-1 u-0 u-1 r/w-1 ? ? ? ?jtagen ? ?tdoen legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-14 unimplemented: read as ? 0 ? bit 13 iolock: peripheral pin select lock bit (1) 1 = peripheral pin select is locked. writes to pps registers is not allowed. 0 = peripheral pin select is not locke d. writes to pps re gisters is allowed. bit 12 pmdlock: peripheral module disable bit (1) 1 = peripheral module is locked. writes to pmd registers is not allowed. 0 = peripheral module is not locked. writes to pmd registers is allowed. bit 11-4 unimplemented: read as ? 0 ? bit 3 jtagen: jtag port enable bit 1 = enable the jtag port 0 = disable the jtag port bit 2-1 unimplemented: read as ? 1 ? bit 0 tdoen: tdo enable for 2-wire jtag 1 = 2-wire jtag protocol uses tdo 0 = 2-wire jtag protocol does not use tdo note 1: to change this bit, the unlock sequence must be performed. refer to section 6. ?oscillator? (ds61112) in the ?pic32 family reference manual? for details. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 234 preliminary ? 2011-2012 microchip technology inc. register 26-6: devid: device and revision id register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 rrrrrrrr ver<3:0> (1) devid<27:24> (1) 23:16 rrrrrrrr devid<23:16> (1) 15:8 rrrrrrrr devid<15:8> (1) 7:0 rrrrrrrr devid<7:0> (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-28 ver<3:0>: revision identifier bits (1) bit 27-0 devid<27:0>: device id (1) note 1: see the ?pic32mx flash programming specification? (ds61145) for a list of revision and device id values. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 235 pic32mx1xx/2xx 26.2 watchdog timer (wdt) this section describes the operation of the wdt and power-up timer of th e pic32mx1xx/2xx. the wdt, when enabled, operates from the internal low-power oscillator (lprc) clock source and can be used to detect system softwa re malfunctions by reset- ting the device if the wdt is not cleared periodically in software. various wdt time-out periods can be selected using the wdt postscaler. the wdt can also be used to wake the device from sleep or idle mode. the following are some of t he key features of the wdt module: ? configuration or software controlled ? user-configurable time-out period ? can wake the device from sleep or idle figure 26-1: watchdog and power-up timer block diagram wake wdtclr = 1 wdt enable lprc power save 25-bit counter pwrt enable wdt enable lprc wdt counter reset control oscillator 25 device reset nmi (wake-up) pwrt pwrt enable fwdtps<4:0> (devcfg1<20:16>) clock decoder 1 1:64 output 0 1 wdt enable reset event www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 236 preliminary ? 2011-2012 microchip technology inc. register 26-7: wdtcon: watc hdog timer control register (1,2,3) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 on (1,2) ? ? ? ? ? ? ? 7:0 u-0 r-y r-y r-y r-y r-y r/w-0 r/w-0 ? swdtps<4:0> wd twinen wdtclr legend: y = values set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: watchdog timer enable bit (1,2) 1 = enables the wdt if it is not enabled by the device configuration 0 = disable the wdt if it was enabled in software bit 14-7 unimplemented: read as ? 0 ? bit 6-2 swdtps<4:0>: shadow copy of watchdog timer postscaler value from device configuration bits on reset, these bits are set to the values of the wdtps <4:0> of configuration bits. bit 1 wdtwinen: watchdog timer window enable bit 1 = enable windowed watchdog timer 0 = disable windowed watchdog timer bit 0 wdtclr: watchdog timer reset bit 1 = writing a ? 1 ? will clear the wdt 0 = software cannot force this bit to a ? 0 ? note 1: a read of this bit results in a ? 1 ? if the watchdog timer is enabled by the device configuration or software. 2: when using the 1:1 pbclk divisor, the user?s software should not read or write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that clears the module?s on bit. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 237 pic32mx1xx/2xx 26.3 on-chip voltage regulator all pic32mx1xx/2xx devices? core and digital logic are designed to operate at a nominal 1.8v. to simplify system designs, most devices in the pic32mx1xx/2xx family incorporate an on-chip regu- lator providing the required core logic voltage from v dd . a low-esr capacitor (such as tantalum) must be connected to the v cap pin (see figure 26-2 ). this helps to maintain the stability of the regulator. the recommended value for the filter capacitor is provided in section 29.1 ?dc characteristics? . 26.3.1 on-chip regulator and por it takes a fixed delay for the on-chip regulator to generate an output. during this time, designated as t pu , code execution is disabled. t pu is applied every time the device resumes operation after any power-down, including sleep mode. 26.3.2 on-chip regulator and bor pic32mx1xx/2xx devices also have a simple brown- out capability. if the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator reset circuitry will generate a brown-out reset. this event is captured by the bor flag bit (rcon<1>). the brown-out voltage levels are specific in section 29.1 ?dc characteristics? . figure 26-2: connections for the on-chip regulator 26.4 programming and diagnostics pic32mx1xx/2xx devices provide a complete range of programming and diagnostic features that can increase the flexibility of any application using them. these features allow syst em designers to include: ? simplified field programmability using two-wire in-circuit serial pr ogramming? (icsp?) interfaces ? debugging using icsp ? programming and debugging capabilities using the ejtag extension of jtag ? jtag boundary scan testing for device and board diagnostics pic32 devices incorporate two programming and diag- nostic modules, and a trace controller, that provide a range of functions to the application developer. figure 26-3: block diagram of programming, debugging and trace ports note: it is important that the low-esr capacitor is placed as close as possible to the v cap pin. v dd v cap v ss pic32 c efc (2,3) 3.3v (1) note 1: these are typical operating voltages. refer to section 29.1 ?dc characteristics? for the full operating ranges of v dd . 2: it is important that the low-esr capacitor is placed as close as possible to the v cap pin. 3: the typical voltage on the v cap pin is 1.8v. (10 f typ) tdi tdo tck tms jtag controller icsp? controller core jtagen debug<1:0> icesel pgec1 pged1 pgec4 pged4 www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 238 preliminary ? 2011-2012 microchip technology inc. notes: www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 239 pic32mx1xx/2xx 27.0 instruction set the pic32mx1xx/2xx family instruction set complies with the mips32 ? release 2 instruction set architec- ture. the pic32 device family does not support the fol- lowing features: ? core extend instructions ? coprocessor 1 instructions ? coprocessor 2 instructions note: refer to ?mips32 ? architecture for programmers volume ii: the mips32 ? instruction set? at www.mips.com for more information. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 240 preliminary ? 2011-2012 microchip technology inc. notes: www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 241 pic32mx1xx/2xx 28.0 development support the pic ? microcontrollers and dspic ? digital signal controllers are supported with a full range of software and hardware development tools: ? integrated development environment - mplab ? ide software ? compilers/assemblers/linkers - mplab c compiler for various device families - hi-tech c ? for various device families - mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/link er/librarian for various device families ? simulators - mplab sim software simulator ? emulators - mplab real ice? in-circuit emulator ? in-circuit debuggers - mplab icd 3 - pickit? 3 debug express ? device programmers - pickit? 2 programmer - mplab pm3 device programmer ? low-cost demonstratio n/development boards, evaluation kits, and starter kits 28.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. the mplab ide is a windows ? operating system-based app lication that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - in-circuit emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select thir d party tools, such as iar c compilers the mplab ide allows you to: ? edit your source files (either c or assembly) ? one-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) ? debug using: - source files (c or assembly) - mixed c and assembly - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 242 preliminary ? 2011-2012 microchip technology inc. 28.2 mplab c compilers for various device families the mplab c compiler code development systems are complete ansi c compilers for microchip?s pic18, pic24 and pic32 families of microcontrollers and the dspic30 and dspic33 families of digital signal control- lers. these compilers provide powerful integration capabilities, superior code optimization and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 28.3 hi-tech c for various device families the hi-tech c compiler code development systems are complete ansi c comp ilers for microchip?s pic family of microcontrollers and the dspic family of digital signal controllers. these compilers provide powerful integration capabilities, omniscient code generation and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. the compilers include a macro assembler, linker, pre- processor, and one-step driver, and can run on multiple platforms. 28.4 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 28.5 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/libra ry features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 28.6 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic devices. mplab c compiler uses the assembler to produce its object file. the assembler generates relocatable objec t files that can then be archived or linked with other relocatable object files and archives to create an execut able file. notable features of the assembler include: ? support for the entire device instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 243 pic32mx1xx/2xx 28.7 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus c ontroller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 28.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs pic ? flash mcus and dspic ? flash dscs with the easy-to-use, powerful graphical user interface of the mplab integrated devel opment environment (ide), included with each kit. the emulator is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in- circuit debugger systems (rj11) or with the new high- speed, noise tolerant, low-voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added. mplab real ice offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 28.9 mplab icd 3 in-circuit debugger system mplab icd 3 in-circuit debugger system is micro- chip's most cost effective high-speed hardware debugger/programmer for microchip flash digital sig- nal controller (dsc) and microcontroller (mcu) devices. it debugs and programs pic ? flash microcon- trollers and dspic ? dscs with the powerful, yet easy- to-use graphical user interface of mplab integrated development environment (ide). the mplab icd 3 in-circuit debugger probe is con- nected to the design engineer's pc using a high-speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 28.10 pickit 3 in-circuit debugger/ programmer and pickit 3 debug express the mplab pickit 3 allows debugging and program- ming of pic ? and dspic ? flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mp lab integrated development environment (ide). the mplab pickit 3 is connected to the design engineer's pc using a full speed usb interface and can be connec ted to the target via an microchip debug (rj-11) connector (compatible with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to imple- ment in-circuit debugging and in-circuit serial pro- gramming?. the pickit 3 debug express include the pickit 3, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 244 preliminary ? 2011-2012 microchip technology inc. 28.11 pickit 2 development programmer/debugger and pickit 2 debug express the pickit? 2 development programmer/debugger is a low-cost development tool with an easy to use inter- face for programming and debugging microchip?s flash families of microcontrollers. the full featured windows ? programming interface supports baseline (pic10f, pic12f5xx, pic16f5xx), midrange (pic12f6xx, pic16f), pic18f, pic24, dspic30, dspic33, and pic32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many microchip serial eeprom products. with microchip?s powerful mplab integrated development environmen t (ide) the pickit? 2 enables in-circuit debugging on most pic ? microcon- trollers. in-circuit-debugging runs, halts and single steps the program while the pic microcontroller is embedded in the applicatio n. when halted at a break- point, the file registers ca n be examined and modified. the pickit 2 debug express include the pickit 2, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. 28.12 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket asse mbly to support various package types. the icsp? ca ble assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc co nnection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorpor ates an mmc card for file storage and data applications. 28.13 demonstration/development boards, evaluation kits, and starter kits a wide variety of demonstr ation, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, sw itches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page ( www.microchip.com ) for the complete list of demonstration, development and evaluation kits. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 245 pic32mx1xx/2xx 29.0 electrical characteristics this section provides an overview of the pic32mx1xx/2xx el ectrical characteristics. additional information will be pro- vided in future revisions of this document as it becomes available. absolute maximum ratings for the pi c32mx1xx/2xx devices are listed below. exposure to these maximum rating conditions for extended periods may affect device reliabili ty. functional operation of the device at these or any other conditions, above the parameters indicated in the operat ion listings of this specification, is not implied. absolute maximum ratings (1) ambient temperature under bias................................................................................................. ............-40c to +105c storage temperature ............................................................................................................ .................. -65c to +150c voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +4.0v voltage on any pin that is not 5v tolerant, with respect to v ss (note 3) ......................................... -0.3v to (v dd + 0.3v) voltage on any 5v tolerant pin with respect to v ss when v dd 2.3v (note 3) ........................................ -0.3v to +5.5v voltage on any 5v tolerant pin with respect to v ss when v dd < 2.3v (note 3) ........................................ -0.3v to +3.6v voltage on d+ or d- pin with respect to v usb 3 v 3 ..................................................................... -0.3v to (v usb 3 v 3 + 0.3v) voltage on v bus with respect to v ss ....................................................................................................... -0.3v to +5.5v maximum current out of v ss pin(s) .......................................................................................................................3 00 ma maximum current into v dd pin(s) (note 2) ............................................................................................................300 ma maximum output current sunk by any i/o pin............. ........................................................................ .....................15 ma maximum output current sourced by any i/o pin .......... ........................................................................ ..................15 ma maximum current sunk by all ports ......................... ..................................................................... .........................200 ma maximum current sourced by all ports (note 2) ....................................................................................................200 ma note 1: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional op eration of the device at t hose or any other conditions, above those indicated in the operatio n listings of this specification, is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 2: maximum allowable current is a function of device maximum power dissipation (see table 29-2 ). 3: see the ? pin diagrams ? section for the 5v tolerant pins. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 246 preliminary ? 2011-2012 microchip technology inc. 29.1 dc characteristics table 29-1: operating mips vs. voltage characteristic v dd range (in volts) temp. range (in c) max. frequency pic32mx1xx/2xx dc5 2.3-3.6v -40c to +85c 40 mhz dc5b 2.3-3.6v -40c to +105c 40 mhz table 29-2: thermal operating conditions rating symbol min. typical max. unit industrial temperature devices operating junction temperature range t j -40 ? +125 c operating ambient temperature range t a -40 ? +85 c v-temp temperature devices operating junction temperature range t j -40 ? +140 c operating ambient temperature range t a -40 ? +105 c power dissipation: internal chip power dissipation: p int = v dd x (i dd ? s i oh ) p d p int + p i / o w i/o pin power dissipation: i/o = s (({v dd ? v oh } x i oh ) + s (v ol x i ol )) maximum allowed power dissipation p dmax (t j ? t a )/ ja w table 29-3: thermal packaging characteristics characteristics symbol typical max. unit notes package thermal resi stance, 28-pin ssop ja 71 ? c/w 1 package thermal resistance, 28-pin soic ja 50 ? c/w 1 package thermal resi stance, 28-pin spdip ja 42 ? c/w 1 package thermal resi stance, 28-pin qfn ja 35 ? c/w 1 package thermal resistance, 36-pin vtla ja 31 ? c/w 1 package thermal resi stance, 44-pin qfn ja 32 ? c/w 1 package thermal resi stance, 44-pin tqfp ja 45 ? c/w 1 package thermal resistance, 44-pin vtla ja 30 ? c/w 1 note 1: junction to ambient thermal resistance, theta- ja ( ja ) numbers are achieved by package simulations. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 247 pic32mx1xx/2xx table 29-5: dc characteristics: operating current (i dd ) table 29-4: dc temperature and voltage specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. typical max. units conditions operating voltage dc10 v dd supply voltage 2.3 ? 3.6 v ? dc12 v dr ram data retention voltage (note 1) 1.75 ? ? v ? dc16 v por v dd start voltage to ensure internal power-on reset signal 1.75 ? 2.1 v ? dc17 s vdd v dd rise rate to ensure internal power-on reset signal 0.00005 ? 0.115 v/ s? note 1: this is the limit to which v dd can be lowered without losing ram data. dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp parameter no. typical (3) max. units conditions operating current (i dd ) (1,2) dc20 2 3 ma 4 mhz (note 4) dc21 7 10.5 ma 10 mhz dc22 10 15 ma 20 mhz (note 4) dc23 15 23 ma 30 mhz (note 4) dc24 20 30 ma 40 mhz dc25 100 150 a +25oc, 3.3v lprc (32 khz) (note 4) note 1: a device?s i dd supply current is mainly a function of t he operating voltage and frequency. other factors, such as pbclk (peripheral bus clock) frequency, num ber of peripheral modules enabled, internal code execution pattern, execution from program flash me mory vs. sram, i/o pin l oading and switching rate, oscillator type, as well as temperature, c an have an impact on the current consumption. 2: the test conditions for i dd measurements are as follows: oscillat or mode is ec (for 8 mhz and below) and ec+pll (for above 8 mhz) with osc1 driven by exter nal square wave from ra il-to-rail. cpu, program flash and sram data memory are operational. a ll peripheral modules are disabled (on bit = 0 ) but the associated pmd bit is cleared. wdt and fscm are dis abled. all i/o pins are configured as inputs and pulled to v ss . mclr = v dd . 3: data in ?typical? column is at 3.3v, 25c at s pecified operating frequency un less otherwise stated. parameters are for design guidance only and are not tested. 4: this parameter is characterized, but not tested in manufacturing. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 248 preliminary ? 2011-2012 microchip technology inc. table 29-6: dc characteristics: idle current (i idle ) dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp parameter no. typical (2) max. units conditions idle current (i idle ): core off, clock on base current (note 1) dc30a 1 1.5 ma 4 mhz (note 3) dc31a 2 3 ma 10 mhz dc32a 4 6 ma 20 mhz (note 3) dc33a 5.5 8 ma 30 mhz (note 3) dc34a 7.5 11 ma 40 mhz dc37a 100 ? a -40c 3.3v lprc (31 khz) (note 3) dc37b 250 ? a +25c dc37c 380 ? a +85c note 1: the test conditions for base i dle current measurements are as follows: system clock is enabled and pbclk divisor = 1:1. cpu in idle mode (cpu core halted). all peripheral modules are disabled (on bit = 0), but the associated pmd bit is cleared. wd t and fscm are disabled. all i/o pins are config- ured as inputs and pulled to v ss . mclr = v dd . 2: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: this parameter is characterized, but not tested in manufacturing. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 249 pic32mx1xx/2xx table 29-7: dc characteristics: power-down current (i pd ) dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. typical (2) max. units conditions power-down current (i pd ) (note 1) dc40k 10 16 a-40c base power-down current dc40l 44 70 a+25c dc40n 168 259 a+85c dc40m 335 536 a +105oc module differential current dc41e 5 20 a 3.6v watchdog timer current: i wdt (note 3) dc42e 23 50 a 3.6v rtcc + timer1 w/32 khz crystal: i rtcc (note 3) dc43d 1000 1100 a 3.6v adc: i adc (notes 3,4) note 1: base i pd is measured with all peripheral modules and clocks shut down (on = 0 , pmdx = 1 ), cpu clock is disabled. all i/os are configured as inputs and pulled low. wdt and fscm are disabled. 2: data in the ?typical? column is at 3.3v, 25c unle ss otherwise stated. parameters are for design guidance only and are not tested. 3: the current is the additional current consumed when the module is enabled. this current should be added to the base i pd current. 4: test conditions for adc module differential current are as follows: internal adc rc oscillator enabled. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 250 preliminary ? 2011-2012 microchip technology inc. table 29-8: dc characteristics: i/o pin input specifications dc characteristics standard operating conditions: 2. 3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. typical (1) max. units conditions v il input low voltage di10 i/o pins with pmp v ss ?0.15v dd v i/o pins v ss ?0.2v dd v di18 sdax, sclx v ss ?0.3v dd v smbus disabled (note 4) di19 sdax, sclx v ss ? 0.8 v smbus enabled (note 4) v ih input high voltage di20 i/o pins not 5v-tolerant (5) 0.65 v dd ?v dd v (note 4) i/o pins 5v-tolerant with pmp (5) 0.25 v dd + 0.8v ? 5.5 v (note 4) i/o pins 5v-tolerant (5) 0.65 v dd ?5.5v di28 sdax, sclx 0.65 v dd ? 5.5 v smbus disabled (note 4) di29 sdax, sclx 2.1 ? 5.5 v smbus enabled, 2.3v v pin 5.5 (note 4) di30 i cnpu change notification pull-up current 50 250 400 av dd = 3.3v, v pin = v ss di31 i cnpd change notification pull-down current (4) ?50?av dd = 3.3v, v pin = v dd i il input leakage current (note 3) di50 i/o ports ? ? + 1 av ss v pin v dd , pin at high-impedance di51 analog input pins ? ? + 1 av ss v pin v dd , pin at high-impedance di55 mclr (2) ??+ 1 av ss v pin v dd di56 osc1 ? ? + 1 av ss v pin v dd , xt and hs modes note 1: data in ?typical? column is at 3.3v, 25c unless other wise stated. parameters are for design guidance only and are not tested. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher le akage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: this parameter is characterized, but not tested in manufacturing. 5: see the ?pin diagrams? section for the 5v-tolerant pins. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 251 pic32mx1xx/2xx table 29-9: dc characteristics: i/o pin output specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. symbol characteristic mi n. typ. max. units conditions do10 v ol output low voltage i/o pins ??0.4v i ol 10 ma, v dd = 3.3v do20 v oh output high voltage i/o pins 1.5 (1) ?? v i oh -14 ma, v dd = 3.3v 2.0 (1) ?? i oh -12 ma, v dd = 3.3v 2.4 ? ? i oh -10 ma, v dd = 3.3v 3.0 (1) ?? i oh -7 ma, v dd = 3.3v note 1: parameters are characterized, but not tested. table 29-10: electrical characteristics: bor dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. (1) typical max. units conditions bo10 v bor bor event on v dd transition high-to-low 2.0 ? 2.3 v ? note 1: parameters are for design guidance only and are not tested in manufacturing. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 252 preliminary ? 2011-2012 microchip technology inc. table 29-11: dc characteristics: program memory (3) dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. typical (1) max. units conditions program flash memory d130 e p cell endurance 20,000 ? ? e/w ? d131 v pr v dd for read 2.3 ? 3.6 v ? d132 v pew v dd for erase or write 2.3 ? 3.6 v ? d134 t retd characteristic retention 20 ? ? year p rovided no other specifications are violated d135 i ddp supply current during programming ?10 ?ma ? t ww word write cycle time 20 ? 40 s ? d136 t rw row write cycle time (note 2) (128 words per row) 34.5?ms ? d137 t pe page erase cycle time 20 ? ? ms ? t ce chip erase cycle time 80 ? ? ms ? note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. 2: the minimum sysclk for row programming is 4 mhz. care should be taken to mi nimize bus activities during row programming, such as suspending any me mory-to-memory dma operations. if heavy bus loads are expected, selecting bus matrix arbitration mode 2 (rotating priority) may be necessary. the default arbitration mode is mode 1 (cpu has lowest priority). 3: refer to the ?pic32 flash progra mming specification? (ds61145) for operating conditions during programming and erase cycles. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 253 pic32mx1xx/2xx table 29-12: comparator specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. typical max. units comments d300 v ioff input offset voltage ? 7.5 25 mv a vdd = v dd , a vss = v ss d301 v icm input common mode voltage 0 ? v dd va vdd = v dd , a vss = v ss (note 2) d302 cmrr common mode rejection ratio 55 ? ? db max v icm = (v dd - 1)v (note 2) d303 t resp response time ? 150 400 ns av dd = v dd , av ss = v ss (notes 1,2) d304 on2 ov comparator enabled to output valid ??10 s comparator module is configured before setting the comparator on bit (note 2) d305 iv ref internal voltage referenc e 1.14 1.2 1.26 v bgsel<1:0> = 00 d312 t set internal voltage reference setting time (note 3) ??10s ? note 1: response time measured with one comparator input at (v dd ? 1.5)/2, while the other input transitions from v ss to v dd . 2: these parameters are characterized but not tested. 3: settling time measured while cvrr = 1 and cvr<3:0> transitions from ? 0000 ? to ? 1111 ?. this parameter is characterized, but not tested in manufacturing. table 29-13: internal voltage regulator specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. typical max. units comments d321 c efc external filter capacitor value 8 10 ? f capacitor must be low series resistance (1 ohm). typical voltage on the v cap pin is 1.8v. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 254 preliminary ? 2011-2012 microchip technology inc. 29.2 ac characteristics and timing parameters the information contained in this section defines pic32mx1xx/2xx ac char acteristics and timing parameters. figure 29-1: load conditions for device timing specifications figure 29-2: external clock timing v dd /2 c l r l pin pin v ss v ss c l r l =464 c l = 50 pf for all pins 50 pf for osc2 pin (ec mode) load condition 1 ? for all pins except osc2 load condition 2 ? for osc2 table 29-14: capacitive loading requirements on output pins ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. typical (1) max. units conditions do56 c io all i/o pins and osc2 ? ? 50 pf ec mode do58 c b sclx, sdax ? ? 400 pf in i 2 c? mode note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. osc1 os20 os30 os30 os31 os31 www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 255 pic32mx1xx/2xx table 29-15: external clock timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. typical (1) max. units conditions os10 f osc external clki frequency (external clocks allowed only in ec and ecpll modes) dc 4 ? ? 40 40 mhz mhz ec (note 4) ecpll (note 3) os11 oscillator crystal frequency 3 ? 10 mhz xt (note 4) os12 4 ? 10 mhz xtpll (notes 3,4) os13 10 ? 25 mhz hs (note 5) os14 10 ? 25 mhz hspll (notes 3,4) os15 32 32.768 100 khz s osc (note 4) os20 t osc t osc = 1/f osc = t cy (note 2) ? ? ? ? see parameter os10 for f osc value os30 t os l, t os h external clock in (osc1) high or low time 0.45 x t osc ??nsec (note 4) os31 t os r, t os f external clock in (osc1) rise or fall time ? ? 0.05 x t osc ns ec (note 4) os40 t ost oscillator start-up timer period (only applies to hs, hspll, xt, xtpll and s osc clock oscillator modes) ?1024?t osc (note 4) os41 t fscm primary clock fail safe time-out period ?2?ms (note 4) os42 g m external oscillator transconductance ?12?ma/vv dd = 3.3v, t a = +25c (note 4) note 1: data in ?typical? column is at 3.3v, 25c unless othe rwise stated. parameters are characterized but are not tested. 2: instruction cycle period (t cy ) equals the input oscillator time base period. all specified values are based on characterization data for that particular oscillator ty pe under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osc1/clki pin. 3: pll input requirements: 4 mh z f pllin 5 mh z (use pll prescaler to reduce f osc ). this parameter is characterized, but tested at 10 mhz only at manufacturing. 4: this parameter is characterized, but not tested in manufacturing. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 256 preliminary ? 2011-2012 microchip technology inc. table 29-16: pll clock timing specifications ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. typical max. units conditions os50 f plli pll voltage controlled oscillator (vco) input frequency range 3.92 ? 5 mhz ecpll, hspll, xtpll, frcpll modes os51 f sys on-chip vco system frequency 60 ? 120 mhz ? os52 t lock pll start-up time (lock time) ? ? 2 ms ? os53 d clk clko stability (2) (period jitter or cumulative) -0.25 ? +0.25 % measured over 100 ms period note 1: these parameters are characterized, but not tested in manufacturing. 2: this jitter specification is based on clock-cycle by cl ock-cycle measurements. to get the effective jitter for individual time-bases on communicat ion clocks, use t he following formula: for example, if sysclk = 40 mhz and spi bit rate = 20 mhz, the effective jitter is as follows: effectivejitter d clk sysclk communicationclock --------------------------------------------------------- - -------------------------------------------------------------- = effectivejitter d clk 40 20 ----- - ------------- - d clk 1.41 ------------- - == table 29-17: internal frc accuracy ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. characteristics min. typical max. units conditions internal frc accuracy @ 8.00 mhz (1) f20b frc -0.9 ? +0.9 % ? note 1: frequency calibrated at 25c and 3.3v. the tun bits can be used to compensate for temperature drift. table 29-18: internal lprc accuracy ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. characteristics min. typical max. units conditions lprc @ 31.25 khz (1) f21 lprc -15 ? +15 % ? note 1: change of lprc frequency as v dd changes. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 257 pic32mx1xx/2xx figure 29-3: i/o timing characteristics note: refer to figure 29-1 for load conditions. i/o pin (input) i/o pin (output) di35 di40 do31 do32 table 29-19: i/o timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (2) min. typical (1) max. units conditions do31 t io r port output rise time ? 5 15 ns v dd < 2.5v ?510nsv dd > 2.5v do32 t io f port output fall time ? 5 15 ns v dd < 2.5v ?510nsv dd > 2.5v di35 t inp intx pin high or low time 10 ? ? ns ? di40 t rbp cnx high or low time (input) 2 ? ? t sysclk ? note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. 2: this parameter is characterized, but not tested in manufacturing. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 258 preliminary ? 2011-2012 microchip technology inc. figure 29-4: power-on reset timing characteristics v dd v por note 1: the power-up period will be extended if the power-up sequence completes before the device exits from bor (v dd < v ddmin ). 2: includes interval voltage regulator stabilization delay. sy00 power-up sequence (note 2) internal voltage regulator enabled (t pu ) sy10 cpu starts fetching code clock sources = (hs, h spll, xt, xtpll and s osc ) v dd v por sy00 power-up sequence (note 2) internal voltage regulator enabled (t pu ) (t sysdly ) cpu starts fetching code (note 1) (note 1) clock sources = (frc, frcdiv, frcdi v16, frcpll, ec, ecpll and lprc) (t ost ) sy02 (t sysdly ) sy02 www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 259 pic32mx1xx/2xx figure 29-5: external reset timing characteristics table 29-20: resets timing ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. typical (2) max. units conditions sy00 t pu power-up period internal voltage regulator enabled ?400600 s ? sy02 t sysdly system delay period: time required to reload device configuration fuses plus sysclk delay before first instruction is fetched. ? 1 s + 8 sysclk cycles ?? ? sy20 t mclr mclr pulse width (low) 2 ? ? s ? sy30 t bor bor pulse width (low) ? 1 ? s? note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. characterized by design but not tested. mclr (sy20) reset sequence (sy10) cpu starts fetching code bor (sy30) t ost t mclr t bor reset sequence cpu starts fetching code clock sources = (frc, f rcdiv, frcdiv16, frcpll , ec, ecpll and lprc) clock sources = (hs, h spll, xt, xtpll and s osc ) (t sysdly ) sy02 (t sysdly ) sy02 www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 260 preliminary ? 2011-2012 microchip technology inc. figure 29-6: timer1, 2, 3, 4, 5 externa l clock timing characteristics note: refer to figure 29-1 for load conditions. tx11 tx15 tx10 tx20 tmrx os60 txck table 29-21: timer1 external clock timing requirements (1) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (2) min. typical max. units conditions ta10 t tx htxck high time synchronous, with prescaler [(12.5 ns or 1 t pb )/n] + 25 ns ? ? ns must also meet parameter ta15 asynchronous, with prescaler 10 ? ? ns ? ta11 t tx ltxck low time synchronous, with prescaler [(12.5 ns or 1 t pb )/n] + 25 ns ? ? ns must also meet parameter ta15 asynchronous, with prescaler 10 ? ? ns ? ta15 t tx ptxck input period synchronous, with prescaler [(greater of 25 ns or 2 t pb )/n] + 30 ns ??nsv dd > 2.7v [(greater of 25 ns or 2 t pb )/n] + 50 ns ??nsv dd < 2.7v asynchronous, with prescaler 20 ? ? ns v dd > 2.7v (note 3) 50 ? ? ns v dd < 2.7v (note 3) os60 f t 1 sosc1/t1ck oscillator input frequency range (oscillator enabled by setting tcs bit (t1con<1>)) 32 ? 100 khz ? ta20 t ckextmrl delay from external txck clock edge to timer increment ?1t pb ? note 1: timer1 is a type a. 2: this parameter is characterized, but not tested in manufacturing. 3: n = prescale value (1, 8, 64, 256). www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 261 pic32mx1xx/2xx figure 29-7: input capture (capx) timing characteristics table 29-22: timer2, 3, 4, 5 external clock timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. max. units conditions tb10 t tx htxck high time synchronous, with prescaler [(12.5 ns or 1 t pb )/n] + 25 ns ? ns must also meet parameter tb15 n = prescale value (1, 2, 4, 8, 16, 32, 64, 256) tb11 t tx ltxck low time synchronous, with prescaler [(12.5 ns or 1 t pb )/n] + 25 ns ? ns must also meet parameter tb15 tb15 t tx ptxck input period synchronous, with prescaler [(greater of [(25 ns or 2 t pb )/n] + 30 ns ?nsv dd > 2.7v [(greater of [(25 ns or 2 t pb )/n] + 50 ns ?nsv dd < 2.7v tb20 t ckextmrl delay from external txck clock edge to timer increment ?1t pb ? note 1: these parameters are characterized, but not tested in manufacturing. icx ic10 ic11 ic15 note: refer to figure 29-1 for load conditions. table 29-23: input capture module timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. max. units conditions ic10 t cc l icx input low time [(12.5 ns or 1 t pb )/n] + 25 ns ? ns must also meet parameter ic15. n = prescale value (1, 4, 16) ic11 t cc h icx input high time [(12.5 ns or 1 t pb )/n] + 25 ns ? ns must also meet parameter ic15. ic15 t cc p icx input period [(25 ns or 2 t pb )/n] + 50 ns ?ns ? note 1: these parameters are characterized, but not tested in manufacturing. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 262 preliminary ? 2011-2012 microchip technology inc. figure 29-8: output compare module (ocx) timing characteristics table 29-24: output compare module timing requirements figure 29-9: ocx/pwm module timing characteristics ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. typical (2) max. units conditions oc10 t cc f ocx output fall time ? ? ? ns see parameter do32 oc11 t cc r ocx output rise time ? ? ? ns see parameter do31 note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless othe rwise stated. parameters ar e for design guidance only and are not tested. ocx oc11 oc10 (output compare note: refer to figure 29-1 for load conditions. or pwm mode) ocfa/ocfb ocx oc20 oc15 note: refer to figure 29-1 for load conditions. ocx is tri-stated table 29-25: simple ocx/pwm mode timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param no. symbol characteristics (1) min typical (2) max units conditions oc15 t fd fault input to pwm i/o change ? ? 50 ns ? oc20 t flt fault input pulse width 50 ? ? ns ? note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless other wise stated. parameters are for design guidance only and are not tested. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 263 pic32mx1xx/2xx figure 29-10: spix module master mode (cke = 0 ) timing characteristics table 29-26: spix master mode (cke = 0 ) timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. typical (2) max. units conditions sp10 t sc l sckx output low time (note 3) t sck /2 ? ? ns ? sp11 t sc h sckx output high time (note 3) t sck /2 ??ns ? sp20 t sc f sckx output fall time (note 4) ???ns see parameter do32 sp21 t sc r sckx output rise time (note 4) ? ?? ns see parameter do31 sp30 t do f sdox data output fall time (note 4) ? ?? ns see parameter do32 sp31 t do r sdox data output rise time (note 4) ? ?? ns see parameter do31 sp35 t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge ?? 15 ns v dd > 2.7v ?? 20 ns v dd < 2.7v sp40 t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 10 ??ns ? sp41 t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 10 ??ns ? note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 50 ns. therefor e, the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp11 sp10 sp40 sp41 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 msb in lsb in bit 14 - - - -1 sp30 sp31 note: refer to figure 29-1 for load conditions. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 264 preliminary ? 2011-2012 microchip technology inc. figure 29-11: spix module master mode (cke = 1 ) timing characteristics table 29-27: spix module master mode (cke = 1 ) timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. typ. (2) max. units conditions sp10 t sc l sckx output low time (note 3) t sck /2 ? ? ns ? sp11 t sc h sckx output high time (note 3) t sck /2 ? ? ns ? sp20 t sc f sckx output fall time (note 4) ? ? ? ns see parameter do32 sp21 t sc r sckx output rise time (note 4) ? ? ? ns see parameter do31 sp30 t do f sdox data output fall time (note 4) ? ? ? ns see parameter do32 sp31 t do r sdox data output rise time (note 4) ? ? ? ns see parameter do31 sp35 t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge ??15nsv dd > 2.7v ??20nsv dd < 2.7v sp36 t do v2 sc , t do v2 sc l sdox data output setup to first sckx edge 15 ? ? ns ? sp40 t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 15 ? ? ns v dd > 2.7v 20 ? ? ns v dd < 2.7v sp41 t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 15 ? ? ns v dd > 2.7v 20 ? ? ns v dd < 2.7v note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless ot herwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 50 ns. therefor e, the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sdi x sp36 sp30,sp31 sp35 msb bit 14 - - - - - -1 lsb in bit 14 - - - -1 lsb note: refer to figure 29-1 for load conditions. sp11 sp10 sp21 sp20 sp40 sp41 sp20 sp21 msb in www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 265 pic32mx1xx/2xx figure 29-12: spix module slave mode (cke = 0 ) timing characteristics ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sp50 sp40 sp41 sp30,sp31 sp51 sp35 msb lsb bit 14 - - - - - -1 bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp71 sp70 note: refer to figure 29-1 for load conditions. sdi x msb in table 29-28: spix module slave mode (cke = 0 ) timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. typ. (2) max. units conditions sp70 t sc l sckx input low time (note 3) t sck /2 ? ? ns ? sp71 t sc h sckx input high time (note 3) t sck /2 ? ? ns ? sp72 t sc f sckx input fall time ? ? ? ns see parameter do32 sp73 t sc r sckx input rise time ? ? ? ns see parameter do31 sp30 t do f sdox data output fall time (note 4) ? ? ? ns see parameter do32 sp31 t do r sdox data output rise time (note 4) ? ? ? ns see parameter do31 sp35 t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge ??15nsv dd > 2.7v ??20nsv dd < 2.7v sp40 t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 10 ? ? ns ? sp41 t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 10 ? ? ns ? sp50 t ss l2 sc h, t ss l2 sc l ssx to sckx or sckx input 175 ? ? ns ? sp51 t ss h2 do z ssx to sdox output high-impedance (note 3) 5?25ns ? sp52 t sc h2 ss h t sc l2 ss h ssx after sckx edge t sck + 20 ? ? ns ? note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless ot herwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 50 ns. 4: assumes 50 pf load on all spix pins. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 266 preliminary ? 2011-2012 microchip technology inc. figure 29-13: spix module slave mode (cke = 1 ) timing characteristics ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdi sp60 sdix sp30,sp31 msb bit 14 - - - - - -1 lsb sp51 msb in bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp71 sp40 sp41 note: refer to figure 29-1 for load conditions. sp50 sp70 sp35 table 29-29: spix module slave mode (cke = 1 ) timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. typical (2) max. units conditions sp70 t sc l sckx input low time (note 3) t sck /2 ? ? ns ? sp71 t sc h sckx input high time (note 3) t sck /2 ? ? ns ? sp72 t sc f sckx input fall time ? 5 10 ns ? sp73 t sc r sckx input rise time ? 5 10 ns ? sp30 t do f sdox data output fall time (note 4) ? ? ? ns see parameter do32 sp31 t do r sdox data output rise time (note 4) ? ? ? ns see parameter do31 sp35 t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge ? ? 20 ns v dd > 2.7v ? ? 30 ns v dd < 2.7v sp40 t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 10 ? ? ns ? sp41 t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 10 ? ? ns ? sp50 t ss l2 sc h, t ss l2 sc l ssx to sckx or sckx input 175 ? ? ns ? note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless othe rwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 50 ns. 4: assumes 50 pf load on all spix pins. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 267 pic32mx1xx/2xx sp51 t ss h2 do z ssx to sdo x output high-impedance (note 4) 5 ? 25 ns ? sp52 t sc h2 ss h t sc l2 ss h ssx after sckx edge t sck + 20 ??ns ? sp60 t ss l2 do v sdox data output valid after ssx edge ? ? 25 ns ? table 29-29: spix module slave mode (cke = 1 ) timing requirements (continued) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. typical (2) max. units conditions note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless othe rwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 50 ns. 4: assumes 50 pf load on all spix pins. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 268 preliminary ? 2011-2012 microchip technology inc. figure 29-14: i2cx bus start/stop bits timing characteristics (master mode) figure 29-15: i2cx bus data timing characteristics (master mode) sclx sdax start condition stop condition note: refer to figure 29-1 for load conditions. im30 im31 im34 im33 im11 im10 im33 im11 im10 im20 im26 im25 im40 im40 im45 im21 sclx sdax in sdax out note: refer to figure 29-1 for load conditions. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 269 pic32mx1xx/2xx table 29-30: i2cx bus data timing requirements (master mode) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. (1) max. units conditions im10 t lo : scl clock low time 100 khz mode t pb * (brg + 2) ? s? 400 khz mode t pb * (brg + 2) ? s? 1 mhz mode (note 2) t pb * (brg + 2) ? s? im11 t hi : scl clock high time 100 khz mode t pb * (brg + 2) ? s? 400 khz mode t pb * (brg + 2) ? s? 1 mhz mode (note 2) t pb * (brg + 2) ? s? im20 t f : scl sdax and sclx fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (note 2) ? 100 ns im21 t r : scl sdax and sclx rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (note 2) ? 300 ns im25 t su : dat data input setup time 100 khz mode 250 ? ns ? 400 khz mode 100 ? ns 1 mhz mode (note 2) 100 ? ns im26 t hd : dat data input hold time 100 khz mode 0 ? s? 400 khz mode 0 0.9 s 1 mhz mode (note 2) 0 0.3 s im30 t su : sta start condition setup time 100 khz mode t pb * (brg + 2) ? s only relevant for repeated start condition 400 khz mode t pb * (brg + 2) ? s 1 mhz mode (note 2) t pb * (brg + 2) ? s im31 t hd : sta start condition hold time 100 khz mode t pb * (brg + 2) ? s after this period, the first clock pulse is generated 400 khz mode t pb * (brg + 2) ? s 1 mhz mode (note 2) t pb * (brg + 2) ? s im33 t su : sto stop condition setup time 100 khz mode t pb * (brg + 2) ? s? 400 khz mode t pb * (brg + 2) ? s 1 mhz mode (note 2) t pb * (brg + 2) ? s im34 t hd : sto stop condition 100 khz mode t pb * (brg + 2) ? ns ? hold time 400 khz mode t pb * (brg + 2) ? ns 1 mhz mode (note 2) t pb * (brg + 2) ? ns note 1: brg is the value of the i 2 c? baud rate generator. 2: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only). 3: the typical value for this parameter is 104 ns. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 270 preliminary ? 2011-2012 microchip technology inc. im40 t aa : scl output valid from clock 100 khz mode ? 3500 ns ? 400 khz mode ? 1000 ns ? 1 mhz mode (note 2) ? 350 ns ? im45 t bf : sda bus free time 100 khz mode 4.7 ? s the amount of time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s 1 mhz mode (note 2) 0.5 ? s im50 c b bus capacitive loading ? 400 pf ? im51 t pgd pulse gobbler delay 52 312 ns see note 3 table 29-30: i2cx bus data timing requirements (master mode) (continued) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. (1) max. units conditions note 1: brg is the value of the i 2 c? baud rate generator. 2: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only). 3: the typical value for this parameter is 104 ns. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 271 pic32mx1xx/2xx figure 29-16: i2cx bus start/stop bits timing characteristics (slave mode) figure 29-17: i2cx bus data timing characteristics (slave mode) is34 sclx sdax start condition stop condition is33 note: refer to figure 29-1 for load conditions. is31 is30 is30 is31 is33 is11 is10 is20 is26 is25 is40 is40 is45 is21 sclx sdax in sdax out note: refer to figure 29-1 for load conditions. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 272 preliminary ? 2011-2012 microchip technology inc. table 29-31: i2cx bus data timing requirements (slave mode) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. max. units conditions is10 t lo : scl clock low time 100 khz mode 4.7 ? s pbclk must operate at a minimum of 800 khz 400 khz mode 1.3 ? s pbclk must operate at a minimum of 3.2 mhz 1 mhz mode (note 1) 0.5 ? s? is11 t hi : scl clock high time 100 khz mode 4.0 ? s pbclk must operate at a minimum of 800 khz 400 khz mode 0.6 ? s pbclk must operate at a minimum of 3.2 mhz 1 mhz mode (note 1) 0.5 ? s? is20 t f : scl sdax and sclx fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (note 1) ?100ns is21 t r : scl sdax and sclx rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (note 1) ?300ns is25 t su : dat data input setup time 100 khz mode 250 ? ns ? 400 khz mode 100 ? ns 1 mhz mode (note 1) 100 ? ns is26 t hd : dat data input hold time 100 khz mode 0 ? ns ? 400 khz mode 0 0.9 s 1 mhz mode (note 1) 00.3 s is30 t su : sta start condition setup time 100 khz mode 4700 ? ns only relevant for repeated start condition 400 khz mode 600 ? ns 1 mhz mode (note 1) 250 ? ns is31 t hd : sta start condition hold time 100 khz mode 4000 ? ns after this period, the first clock pulse is generated 400 khz mode 600 ? ns 1 mhz mode (note 1) 250 ? ns is33 t su : sto stop condition setup time 100 khz mode 4000 ? ns ? 400 khz mode 600 ? ns 1 mhz mode (note 1) 600 ? ns note 1: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only). www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 273 pic32mx1xx/2xx is34 t hd : sto stop condition hold time 100 khz mode 4000 ? ns ? 400 khz mode 600 ? ns 1 mhz mode (note 1) 250 ns is40 t aa : scl output valid from clock 100 khz mode 0 3500 ns ? 400 khz mode 0 1000 ns 1 mhz mode (note 1) 0350ns is45 t bf : sda bus free time 100 khz mode 4.7 ? s the amount of time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s 1 mhz mode (note 1) 0.5 ? s is50 c b bus capacitive loading ? 400 pf ? table 29-31: i2cx bus data timing requirements (slave mode) (continued) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. max. units conditions note 1: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only). www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 274 preliminary ? 2011-2012 microchip technology inc. table 29-32: adc module specifications ac characteristics standard operating conditions: 2.5v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. typical max. units conditions device supply ad01 av dd module v dd supply greater of v dd ? 0.3 or 2.5 ? lesser of v dd + 0.3 or 3.6 v ? ad02 av ss module v ss supply v ss ?v ss + 0.3 v ? reference inputs ad05 v refh reference voltage high av ss + 2.0 ? av dd v (note 1) ad05a 2.5 ? 3.6 v v refh = av dd (note 3) ad06 v refl reference voltage low av ss ?v refh ? 2.0 v (note 1) ad07 v ref absolute reference voltage (v refh ? v refl ) 2.0 ? av dd v (note 3) ad08 i ref current drain ? 250 ? 400 3 a a adc operating adc off analog input ad12 v inh -v inl full-scale input span v refl ?v refh v? ad13 v inl absolute v inl input voltage av ss ? 0.3 ? av dd /2 v ? ad14 v in absolute input voltage av ss ? 0.3 ? av dd + 0.3 v ? ad15 leakage current ? +/- 0.001 +/-0.610 av inl = av ss = v refl = 0v, av dd = v refh = 3.3v source impedance = 10 k ad17 r in recommended impedance of analog voltage source ??5k (note 1) adc accuracy ? measurements with external v ref +/v ref - ad20c nr resolution 10 data bits bits ? ad21c inl integral nonlinearity > -1 ? < 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.3v ad22c dnl differential nonlinearity > -1 ? < 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.3v (note 2) ad23c g err gain error > -1 ? < 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.3v ad24n e off offset error > -1 ? < 1 lsb v inl = av ss = 0v, av dd = 3.3v ad25c ? monotonicity ? ? ? ? guaranteed note 1: these parameters are not characteri zed or tested in manufacturing. 2: with no missing codes. 3: these parameters are characterized, but not tested in manufacturing. 4: characterized with a 1 khz sine wave. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 275 pic32mx1xx/2xx adc accuracy ? measurements with internal v ref +/v ref - ad20d nr resolution 10 data bits bits (note 3) ad21d inl integral nonlinearity > -1 ? < 1 lsb v inl = av ss = 0v, av dd = 2.5v to 3.6v (note 3) ad22d dnl differential nonlinearity > -1 ? < 1 lsb v inl = av ss = 0v, av dd = 2.5v to 3.6v (notes 2,3) ad23d g err gain error > -4 ? < 4 lsb v inl = av ss = 0v, av dd = 2.5v to 3.6v (note 3) ad24d e off offset error > -2 ? < 2 lsb v inl = av ss = 0v, av dd = 2.5v to 3.6v (note 3) ad25d ? monotonicity ? ? ? ? guaranteed dynamic performance ad31b sinad signal to noise and distortion 55 58.5 ? db (notes 3,4) ad34b enob effective number of bits 9.0 9.5 ? bits (notes 3,4) table 29-32: adc module specifications (continued) ac characteristics standard operating conditions: 2.5v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. typical max. units conditions note 1: these parameters are not characteri zed or tested in manufacturing. 2: with no missing codes. 3: these parameters are characterized, but not tested in manufacturing. 4: characterized with a 1 khz sine wave. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 276 preliminary ? 2011-2012 microchip technology inc. table 29-33: 10-bit conversion rate parameters pic32 10-bit adc conversion rates (2) adc speed t ad min. sampling time min. r s max. v dd temperature adc channels configuration 1 msps to 400 ksps (1) 65 ns 132 ns 500 3.0v to 3.6v -40c to +85c up to 400 ksps 200 ns 200 ns 5.0 k 2.5v to 3.6v -40c to +85c up to 300 ksps 200 ns 200 ns 5.0 k 2.5v to 3.6v -40c to +85c note 1: external v ref - and v ref + pins must be used for correct operation. 2: these parameters are characterized, but not tested in manufacturing. v ref -v ref + adc anx sha ch x v ref -v ref + adc anx sha ch x anx or v ref - or av ss or av dd v ref -v ref + adc anx sha ch x anx or v ref - or av ss or av dd www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 277 pic32mx1xx/2xx table 29-34: analog-to-digital co nversion timing requirements ac characteristics standard operating conditions: 2.5v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. typical (1) max. units conditions clock parameters ad50 t ad adc clock period (2) 65 ? ? ns see table 29-33 conversion rate ad55 tconv conversion time ? 12 t ad ?? ? ad56 f cnv throughput rate (sampling speed) ? ? 1000 ksps av dd = 3.0v to 3.6v ? ? 400 ksps av dd = 2.5v to 3.6v ad57 t samp sample time 1 t ad ???t samp must be 132 ns timing parameters ad60 tpcs conversion start from sample trigger (3) ?1.0 t ad ? ? auto-convert trigger (ssrc<2:0> = 111 ) not selected ad61 tpss sample start from setting sample (samp) bit 0.5 t ad ? 1.5 t ad ?? ad62 tcss conversion completion to sample start (asam = 1 ) (3) ?0.5 t ad ?? ? ad63 tdpu time to stabilize analog stage from adc off to adc on (3) ?? 2 s? note 1: these parameters are characterized, but not tested in manufacturing. 2: because the sample caps will eventually lose char ge, clock rates below 10 khz can affect linearity performance, especially at elevated temperatures. 3: characterized by design but not tested. www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 278 preliminary ? 2011-2012 microchip technology inc. figure 29-18: analog-to-digital co nversion (10-bit mode) timing characteristics (asam = 0 , ssrc<2:0> = 000 ) ad55 t samp clear samp set samp ad61 adclk instruction samp ch0_dischrg ad60 conv adxif buffer( 0 ) buffer( 1 ) 1 2 3 4 5 6 8 5 6 7 1 ? software sets adxcon. samp to start sampling. 2 ? sampling starts after discharge period. t samp is described in section 17. ?10-bit analog-to-digital converter (adc)? 3 ? software clears adxcon. samp to start conversion. 4 ? sampling ends, conversion sequence starts. 5 ? convert bit 9. 8 ? one t ad for end of conversion. ad50 ch0_samp eoc 7 ad55 8 6 ? convert bit 8. 7 ? convert bit 0. execution (ds61104) in the ?pic32 family reference manual? . www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 279 pic32mx1xx/2xx figure 29-19: analog-to-digital conversion (10-bit mode) timing characteristics (chps<1:0> = 01 , asam = 1 , ssrc<2:0> = 111 , samc<4:0> = 00001 ) figure 29-20: parallel slave port timing ad55 t samp set adon adclk instruction samp ch0_dischrg conv adxif buffer( 0 ) buffer( 1 ) 1 2 3 4 5 6 4 5 6 8 1 ? software sets adxcon. adon to start ad operation. 2 ? sampling starts after discharge period. 3 ? convert bit 9. 4 ? convert bit 8. 5 ? convert bit 0. ad50 ch0_samp eoc 7 3 ad55 6 ? one t ad for end of conversion. 7 ? begin conversion of next channel. 8 ? sample for time specified by samc<4:0>. t samp t conv 3 4 execution t samp is described in section 17. ?10-bit analog-to-digital converter (adc)? (ds61104). cs rd wr pmd<7:0> ps1 ps2 ps3 ps4 ps5 ps6 ps7 www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 280 preliminary ? 2011-2012 microchip technology inc. figure 29-21: parallel master port read timing diagram table 29-35: parallel sl ave port requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp para m.no. symbol characteristics (1) min. typ. max. units conditions ps1 tdtv2wr h data in valid before wr or cs inactive (setup time) 20 ? ? ns ? ps2 twrh2dt i wr or cs inactive to data-in invalid (hold time) 40 ? ? ns ? ps3 trdl2dt v rd and cs active to data-out valid ??60ns ? ps4 trdh2dti rd active or cs inactive to data-out invalid 0?10ns ? ps5 tcs cs active time t pb + 40 ? ? ns ? ps6 t wr wr active time t pb + 25 ? ? ns ? ps7 t rd rd active time t pb + 25 ? ? ns ? note 1: these parameters are characterized, but not tested in manufacturing. t pb t pb t pb t pb t pb t pb t pb t pb pb clock pmall/pmalh pmd<7:0> pma<13:18> pmrd pmcs<2:1> pmwr pm5 data address<7:0> pm1 pm3 pm6 data pm7 address<7:0> address pm4 pm2 www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 281 pic32mx1xx/2xx figure 29-22: parallel master port write timing diagram table 29-36: parallel master port read timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. typ. max. units conditions pm1 t lat pmall/pmalh pulse width ? 1 t pb ?? ? pm2 t adsu address out valid to pmall/pmalh invalid (address setup time) ?2 t pb ?? ? pm3 t adhold pmall/pmalh invalid to address out invalid (address hold time) ?1 t pb ?? ? pm4 t ahold pmrd inactive to address out invalid (address hold time) 5??ns ? pm5 t rd pmrd pulse width ? 1 t pb ?? ? pm6 t dsu pmrd or pmenb active to data in valid (data setup time) 15 ? ? ns ? pm7 t dhold pmrd or pmenb inactive to data in invalid (data hold time) ?80?ns ? note 1: these parameters are characterized, but not tested in manufacturing. t pb t pb t pb t pb t pb t pb t pb t pb pb clock pmall/pmalh pmd<7:0> pma<13:18> pmwr pmcs<2:1> pmrd pm12 pm13 pm11 address address<7:0> data pm2 + pm3 pm1 www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 282 preliminary ? 2011-2012 microchip technology inc. table 29-37: parallel master po rt write timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. typ. max. units conditions pm11 t wr pmwr pulse width ? 1 t pb ?? ? pm12 t dvsu data out valid before pmwr or pmenb goes inactive (data setup time) ?2 t pb ?? ? pm13 t dvhold pmwr or pmemb invalid to data out invalid (data hold time) ?1 t pb ?? ? note 1: these parameters are characterized, but not tested in manufacturing. table 29-38: otg electrical specifications ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. typ. max. units conditions usb313 v usb 3 v 3 usb voltage 3.0 ? 3.6 v voltage on v usb 3 v 3 must be in this range for proper usb operation usb315 v ilusb input low voltage for usb buffer ? ? 0.8 v ? usb316 v ihusb input high voltage for usb buffer 2.0 ? ? v ? usb318 v difs differential input sensitivity ? ? 0.2 v the difference between d+ and d- must exceed this value while vcm is met usb319 vcm differential common mode range 0.8 ? 2.5 v ? usb320 z out driver output impedance 28.0 ? 44.0 ? usb321 v ol voltage output low 0.0 ? 0.3 v 14.25 k load connected to 3.6v usb322 v oh voltage output high 2.8 ? 3.6 v 14.25 k load connected to ground note 1: these parameters are characterized, but not tested in manufacturing. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 283 pic32mx1xx/2xx table 29-39: ctmu current source specifications dc characteristics standard oper ating conditions:2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param no. symbol characteristic min. typ. max. units conditions ctmu c urrent s ource ctmui1 i out 1 base range (1) ? 0.55 ? a ctmuicon<9:8> = 01 ctmui2 i out 2 10x range (1) ? 5.5 ? a ctmuicon<9:8> = 10 ctmui3 i out 3 100x range (1) ? 55 ? a ctmuicon<9:8> = 11 ctmui4 i out 4 1000x range (1) ? 550 ? a ctmuicon<9:8> = 00 ctmufv1 v f temperature diode forward voltage (1,2) ?0.598? vt a = +25oc, ctmuicon<9:8> = 01 ?0.658? vt a = +25oc, ctmuicon<9:8> = 10 ?0.721? vt a = +25oc, ctmuicon<9:8> = 11 ctmufv2 v fvr temperature diode rate of change (1,2) ? -1.92 ? mv/oc ctmuicon<9:8> = 01 ? -1.74 ? mv/oc ctmuicon<9:8> = 10 ? -1.56 ? mv/oc ctmuicon<9:8> = 11 note 1: nominal value at center point of cu rrent trim range (ctmuicon<15:10> = 000000 ). 2: parameters are characterized but not tested in manu facturing. measurements taken with the following conditions: ?v ref + = av dd = 3.3v ? adc module configured for conversion speed of 500 ksps ? all pmd bits are cleared (pmdx = 0 ) ? executing a while(1) statement ? device operating from the frc with no pll www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 284 preliminary ? 2011-2012 microchip technology inc. figure 29-23: ejtag timing characteristics t tckeye t tckhigh t tcklow t rf t rf t rf t rf t tsetup t thold t tdoout t tdozstate defined undefined t trst*low t rf tck tdo trst* tdi tms table 29-40: ejtag timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol description (1) min. max. units conditions ej1 t tckcyc tck cycle time 25 ? ns ? ej2 t tckhigh tck high time 10 ? ns ? ej3 t tcklow tck low time 10 ? ns ? ej4 t tsetup tap signals setup time before rising tck 5?ns ? ej5 t thold tap signals hold time after rising tck 3?ns ? ej6 t tdoout tdo output delay time from falling tck ?5ns ? ej7 t tdozstate tdo 3-state delay time from falling tck ?5ns ? ej8 t trstlow trst low time 25 ? ns ? ej9 t rf tap signals rise/fall time, all input and output ??ns ? note 1: these parameters are characterized, but not tested in manufacturing. www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 285 pic32mx1xx/2xx 30.0 dc and ac device characteristics graphs figure 30-1: i/o output voltage high (v oh ) figure 30-2: i/o output voltage low (v ol ) note: the graphs provided following this note ar e a statistical summary based on a limited number of samples and are provided for des ign guidance purposes only. the performance characteristics listed herein are not test ed or guaranteed. in some graphs, the data presented may be out side the specified operating range (e.g., outside specified power supply rang e) and therefore, outsi de the warranted range. -0.050 -0.045 -0.040 -0.035 -0.030 -0.025 -0.020 ioh(a) voh (v) -0.050 -0.045 -0.040 -0.035 -0.030 -0.025 -0.020 -0.015 -0.010 -0.005 0.000 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 ioh(a) voh (v) 3v 3.3v 3.6v absolute maximum 0.015 0.020 0.025 0.030 0.035 0.040 0.045 0.050 ioh(a) vol(v) 0.000 0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0.045 0.050 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 ioh(a) vol(v) v v v www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 286 preliminary ? 2011-2012 microchip technology inc. figure 30-3: typical i pd current @ v dd = 3.3v figure 30-4: typical i dd current @ v dd = 3.3v figure 30-5: typical i idle current @ v dd = 3.3v 150 200 250 300 350 400 i pd (a) 0 50 100 150 200 250 300 350 400 -40-30-20-10 0 102030405060708090100 i pd (a) temperature (celsius) 10 15 20 25 i dd (ma) 0 5 10 15 20 25 0 10203040 i dd (ma) mips 3 4 5 6 7 8 d le current (ma) 0 1 2 0 10203040 i i d mips www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 287 pic32mx1xx/2xx figure 30-6: typical frc frequency @ v dd = 3.3v figure 30-7: typical lprc frequency @ v dd = 3.3v figure 30-8: typical ctmu temperature diode forward voltage 7930 7940 7950 7960 7970 7980 7990 8000 frc frequency (khz) 7900 7910 7920 7930 7940 7950 7960 7970 7980 7990 8000 -40-30-20-10 0 102030405060708090100 frc frequency (khz) temperature (celsius) 31 32 33 lprc frequency (khz) 30 31 32 33 -40-30-20-10 0 102030405060708090100 lprc frequency (khz) temperature (celsius) 0500 0.550 0.600 0.650 0.700 0.750 0.800 0.850 forward voltage (v) 0.350 0.400 0.450 0.500 0.550 0.600 0.650 0.700 0.750 0.800 0.850 -40-30-20-100 102030405060708090100110 forward voltage (v) temperature (celsius) v f = 0.598 v f = 0.658 v f = 0.721 55 a , v f v r = - 1 . 56 m v / o c 5 . 5 a , v f v r = - 1 . 7 4 m v / o c 0 . 5 5 a , v f v r = - 1 . 9 2 m v / o c www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 288 preliminary ? 2011-2012 microchip technology inc. notes: www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 289 pic32mx1xx/2xx 31.0 packaging information 31.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-f ree jedec designator ( ) can be found on the outer packaging for this package. note: if the full microchip part number cannot be mark ed on one line, it is carried over to the next line, thus limiting the number of available ch aracters for customer-specific information. 3 e 3 e example 32mx220f 032be/ml 1130235 3 e 28-lead ssop xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example pic32mx220f 032b-i/ss 1130235 3 e 28-lead soic xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx yywwnnn example pic32mx220f 1130235 032b-i/so 3 e 28-lead qfn xxxxxxxx xxxxxxxx yywwnnn 28-lead spdip xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn example pic32mx220f 1130235 032b-i/sp 3 e www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 290 preliminary ? 2011-2012 microchip technology inc. 31.1 package marking information (continued) xxxxxxxxxx 44-lead qfn xxxxxxxxxx xxxxxxxxxx yywwnnn 32mx220f example 032d-e/ml 1130235 44-lead tqfp xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example 32mx220f 032d-i/pt 1130235 3 e 3 e legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-f ree jedec designator ( ) can be found on the outer packaging for this package. note: if the full microchip part number cannot be mark ed on one line, it is carried over to the next line, thus limiting the number of available ch aracters for customer-specific information. 3 e 3 e 36-lead vtla (tla) xxxxxxxx xxxxxxxx yywwnnn example 32mx220f 032ce/tl 1130235 3 e 44-lead vtla (tla) example xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn pic32 mx120f0 1130235 3 e 32di/tl www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 291 pic32mx1xx/2xx 31.2 package details this section provides the technical details of the packages.
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pic32mx1xx/2xx ds61168d-page 292 preliminary ? 2011-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 293 pic32mx1xx/2xx !
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pic32mx1xx/2xx ds61168d-page 294 preliminary ? 2011-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 295 pic32mx1xx/2xx note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 296 preliminary ? 2011-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 297 pic32mx1xx/2xx
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pic32mx1xx/2xx ds61168d-page 298 preliminary ? 2011-2012 microchip technology inc.
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? 2011-2012 microchip technology inc. preliminary ds61168d-page 299 pic32mx1xx/2xx note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 300 preliminary ? 2011-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 301 pic32mx1xx/2xx 11
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pic32mx1xx/2xx ds61168d-page 302 preliminary ? 2011-2012 microchip technology inc. 11
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? 2011-2012 microchip technology inc. preliminary ds61168d-page 303 pic32mx1xx/2xx 11
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pic32mx1xx/2xx ds61168d-page 304 preliminary ? 2011-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 305 pic32mx1xx/2xx note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 306 preliminary ? 2011-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 307 pic32mx1xx/2xx appendix a: revision history revision a (may 2011) this is the initial released version of this document. revision b (october 2011) the following two global changes are included in this revision: ? all packaging references to vlap have been changed to vtla throughout the document ? all references to v core have been removed ? all occurrences of the ascl1, ascl2, asda1, and asda2 pins have been removed ? v-temp temperature ran ge (-40oc to +105oc) was added to all electrical specification tables this revision includes the addition of the following devices: text and formatting changes were incorporated throughout the document. all other major changes are referenced by their respective section in table a-1 . ? pic32mx130f064b ? pic32mx230f064b ? pic32mx130f064c ? pic32mx230f064c ? pic32mx130f064d ? pic32mx230f064d ? pic32mx150f128b ? pic32mx250f128b ? pic32mx150f128c ? pic32mx250f128c ? pic32mx150f128d ? pic32mx250f128d table a-1: major section updates section name update description ?32-bit microcontro llers (up to 128 kb flash and 32 kb sram) with audio and graphics interfaces, usb, and advanced analog? split the existing features table into two: pic32mx1xx general purpose family features (table 1) and pic32m x2xx usb family features (table 2). added the spdip package reference (see table 1, table 2, and ?pin diagrams? ). added the new devices to the applicable pin diagrams. changed pged2 to pged1 on pin 35 of the 36-pin vtla diagram for pic32mx220f032c, pic32mx220f016c, pic32mx230f064c, and pic32mx250f128c devices. 1.0 ?device overview? added the spdip package reference and updated the pin number for an12 for 44-pin qfn devices in the pinout i/o descriptions (see table 1-1). added the pgec4/pged4 pin pair and updated the c1ina-c1ind and c2ina-c2ind pin numbers for 28-pin ssop/spdip/soic devices in the pinout i/o descriptions (see table 1-1). 2.0 ?guidelines for getting started with 32-bit mi crocontrollers? updated the recommended minimum connection diagram (see figure 2-1). www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 308 preliminary ? 2011-2012 microchip technology inc. 4.0 ?memory organization? added memory maps for the new devices (see figure 4-3 and figure 4-4). removed the bmxchedma bit from t he bus matrix register map (see table 4-1). added the refotrim register, added the divswen bit to the refocon registers, added note 4 to the ulock and soscen bits and added the pbdivrdy bit in the osccon register in the in the system control register map (see table 4-16). removed the alti2c1 and alti2c2 bits from the devcfg3 register and added note 1 to the upllen and up llidiv<2:0> bits of the devcfg2 register in the device configurat ion word summary (see table 4-17). updated note 1 in the device and revision id summary (see table 4-18). added note 2 to the porta register map (see table 4-19). added the ansb6 and ansb12 bits to the anselb register in the portb register map (see table 4-20). added notes 2 and 3 to the portc register map (see table 4-21). updated all register names in the periph eral pin select register map (see table 4-23). added values in support of new devices (16 kb ram and 32 kb ram) in the data ram size register (see register 4-5). added values in support of new devices (64 kb flash and 128 kb flash) in the data ram size regist er (see register 4-5). 8.0 ?oscillator configuration? added note 5 to the pic32mx1xx /2xx family clock diagram (see figure 8-1). added the pbdivrdy bit and note 2 to the oscillator control register (see register 8-1). added the divswen bit and note 3 to the reference oscillator control register (see register 8-3). added the refotrim regi ster (see register 8-4). 21.0 ?10-bit analog-to-digital converter (adc)? updated the adc1 module block diagram (see figure 21-1). updated the notes in the adc input se lect register (see register 21-4). 24.0 ?charge time measurement unit (ctmu)? updated the ctmu block diagram (see figure 24-1). added note 3 to the ctmu control register (see register 24-1) 26.0 ?special features? added note 1 and the pgec4/pged4 pi n pair to the icesel<1:0> bits in devcfg0: device configuration word 0 (see register 26-1). removed the alti2c1 and alti2c2 bits from the device configuration word 3 register (see register 26-4). removed 26.3.3 ?power-up requirements?. added note 3 to the connections for the on-chip regulator diagram (see figure 26-2). updated the block diagram of programming, debugging and trace ports diagram (see figure 26-3). table a-1: major section updates (continued) section name update description www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 309 pic32mx1xx/2xx 29.0 ?electrical characteristics? updated the absolute maximum ratings (removed voltage on v core with respect to v ss ). added the spdip specification to the thermal packaging characteristics (see table 29-2). updated the typical values for para meters dc20-dc24 in the operating current (i dd ) specification (see table 29-5). updated the typical values for parameters dc30a-dc34a in the idle current (i idle ) specification (see table 29-6). updated the typical values for parameters dc40i and dc40n and removed parameter dc40m in t he power-down current (i pd ) specification (see table 29-7). removed parameter d320 (v core ) from the internal voltage regulator specifications and updated the comments (see table 29-13). updated the minimum, typical, and maximum values for parameter f20b in the internal frc accuracy specification (see table 29-17). removed parameter sy01 (t pwrt ) and removed all conditions from resets timing (see table 29-20). updated all parameters in the ctmu specifications (see table 29-39). 31.0 ?packaging information? added the 28-lead spdip package diagram information (see 31.1 ?package marking information? and 31.2 ?package details? ). ?product identification system? added the spdip (sp) package definition. table a-1: major section updates (continued) section name update description www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 310 preliminary ? 2011-2012 microchip technology inc. revision c (november 2011) all major changes are referenced by their respective section in ta b l e a - 2 . revision d (february 2012) all occurrences of v usb were changed to: v usb 3 v 3 . in addition, text and formatting changes were incorporated throughout the document. all other major changes are referenced by their respective section in ta b l e a - 1 . table a-2: major section updates section name update description ?32-bit microcontro llers (up to 128 kb flash and 32 kb sram) with audio and graphics interfaces, usb, and advanced analog? revised the source/sink on i/o pins (see ?input/output? on page 1). added the spdip package to the pic32mx220f032b device in the pic32mx2xx usb family features (see table 2). 4.0 ?memory organization? removed ansb6 from the anselb register and added the odcb6, odcb10, and odcb11 bits in the portb register map (see table 4-20). 29.0 ?electrical characteristics? updated the minimum value for parameter os50 in the pll clock timing specifications (see table 29-16). table a-3: major section updates section name update description ?32-bit microcontrol lers (up to 128 kb flash and 32 kb sram) with audio and graphics interfaces, usb, and advanced analog? corrected a part number error in all pin diagrams. updated the dma channels (programm able/dedicated) column in the pic32mx1xx general purpose family features (see ta b l e 1 ). 1.0 ?device overview? added the tqfp and vtla packages to the 44-pin column heading and updated the pin numbers for the scl1, scl2, sda1, and sda2 pins in the pinout i/o descriptions (see table 1-1 ). 7.0 ?interrupt controller? updated the note that follows the features. updated the interrupt cont roller block diagram (see figure 7-1 ). 29.0 ?electrical characteristics? updated the maximum values for parameters dc20-dc24, and the minimum value for parameter dc21 in the operating current (i dd ) dc characteristics (see table 29-5 ). updated all minimum and maximum values for the idle current (i idle ) dc characteristics (see ta b l e 2 9 - 6 ). updated the maximum values for parameters dc40k, dc40l, dc40n, and dc40m in the power-down current (i pd ) dc characteristics (see table 29-7 ). changed the minimum clock period for sckx from 40 ns to 50 ns in note 3 of the spix master and slave mode timing requirements (see table 29-26 through table 29-29 ). 30.0 ?dc and ac device characteristics graphs? updated the typical i idle current @ v dd = 3.3v graph (see figure 30-5 ). www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 311 pic32mx1xx/2xx index a ac characteristics ............................................................ 254 10-bit conversion rate parameters ......................... 276 adc specifications ................................................... 274 analog-to-digital conversion requirements............. 277 ejtag timing requirements ................................... 284 internal frc accuracy.............................................. 256 internal rc accuracy ................................................ 256 otg electrical specifications ................................... 282 parallel master port read requirements ................. 281 parallel master port write ......................................... 282 parallel master port write requirements.................. 282 parallel slave port requirements ............................. 280 pll clock timing...................................................... 256 analog-to-digital converter (adc).................................... 203 assembler mpasm assembler................................................... 242 b block diagrams adc module.............................................................. 203 comparator i/o operating modes............................. 211 comparator voltage reference ................................ 215 connections for on-chip voltage regulator............. 237 core and peripheral modules ..................................... 19 cpu ............................................................................ 33 ctmu configurations time measurement ........................................... 217 dma .......................................................................... 105 i2c circuit ................................................................. 174 input capture ............................................................ 159 interrupt controller ...................................................... 87 jtag programming, debugging and trace ports .... 237 output compare module........................................... 163 pmp pinout and connections to external devices ... 185 reset system.............................................................. 83 rtcc ........................................................................ 193 spi module ............................................................... 165 timer1....................................................................... 151 timer2/3/4/5 (16-bit) ................................................. 155 typical multiplexed port structure ............................ 143 uart ........................................................................ 179 wdt and power-up timer ........................................ 235 brown-out reset (bor) and on-chip voltage regulator................................ 237 c c compilers mplab c18 .............................................................. 242 charge time measurement unit. see ctmu. clock diagram .................................................................... 96 comparator specifications............................................................ 253 comparator module .......................................................... 211 comparator voltage reference (cvref ............................. 215 configuration bit ............................................................... 225 configuring analog port pins ............................................ 144 cpu architecture overview................................................. 34 coprocessor 0 registers ............................................ 35 core exception types................................................. 36 ejtag debug support ............................................... 36 power management.................................................... 36 cpu module ................................................................. 27, 33 ctmu registers .................................................................. 218 customer change notification service............................. 315 customer notification service .......................................... 315 customer support............................................................. 315 d dc and ac characteristics graphs and tables ................................................... 285 dc characteristics............................................................ 246 i/o pin input specifications ...................................... 250 i/o pin output specifications.................................... 251 idle current (i idle ) .................................................... 248 power-down current (i pd )........................................ 249 program memory...................................................... 252 temperature and voltage specifications.................. 247 development support ....................................................... 241 direct memory access (dma) controller.......................... 105 e electrical characteristics .................................................. 245 ac............................................................................. 254 errata .................................................................................. 16 external clock timer1 timing requirements ................................... 260 timer2, 3, 4, 5 timing requirements ....................... 261 timing requirements ............................................... 255 f flash program memory ...................................................... 79 rtsp operation ......................................................... 79 i i/o ports ........................................................................... 143 parallel i/o (pio) ...................................................... 144 write/read timing.................................................... 144 input change notification ................................................. 144 instruction set................................................................... 239 inter-integrated circuit (i2c .............................................. 173 internal voltage reference specifications........................ 253 internet address ............................................................... 315 interrupt controller.............................................................. 87 irg, vector and bit location ...................................... 88 m memory maps pic32mx11x/21x devices......................................... 38 pic32mx12x/22x devices......................................... 39 pic32mx130/230 devices ......................................... 40 pic32mx150/250 devices ......................................... 41 memory organization ......................................................... 37 layout......................................................................... 37 microchip internet web site.............................................. 315 mplab asm30 assembler, linker, librarian ................... 242 mplab integrated development environment software.. 241 mplab pm3 device programmer .................................... 244 mplab real ice in-circuit emulator system ................ 243 mplink object linker/mplib object librarian ................ 242 o oscillator configuration ...................................................... 95 output compare ............................................................... 163 www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 312 preliminary ? 2011-2012 microchip technology inc. p packaging ......................................................................... 289 details ....................................................................... 291 marking ..................................................................... 289 parallel master port (pmp) ............................................... 185 pic32 family usb interface diagram............................... 122 pinout i/o descriptions (table) ............................................ 20 power-on reset (por) and on-chip voltage regulator ................................ 237 power-saving features..................................................... 221 cpu halted methods ................................................ 221 operation .................................................................. 221 with cpu running..................................................... 221 r reader response ............................................................. 316 real-time clock and calendar (rtcc)............................ 193 register maps ............................................................... 42?70 registers [ pin name ]r (peripheral pin select input)................. 149 ad1chs (adc input select) .................................... 209 ad1con1 (a/d control 1) ........................................ 201 ad1con1 (adc control 1) .............................. 201, 205 ad1con2 (adc control 2) ...................................... 207 ad1con3 (adc control 3) ...................................... 208 ad1cssl (adc input scan select) ......................... 210 alrmdate (alarm date value) ............................... 201 alrmdateclr (alrmdate clear)....................... 201 alrmdateset (alrmdate set) .......................... 201 alrmtime (alarm time value) ............................... 200 alrmtimeclr (alrmtime clear)......................... 201 alrmtimeinv (alrmtime invert) ......................... 201 alrmtimeset (alrmtime set) ............................ 201 bmxbootsz (boot flash (ifm) size ........................ 78 bmxcon (bus matrix configuration) ......................... 73 bmxdkpba (data ram kernel program base address) .................................................... 74 bmxdrmsz (data ram size register) ..................... 77 bmxdudba (data ram user data base address) ... 75 bmxdupba (data ram user program base address) .................................................... 76 bmxpfmsz (program flash (pfm) size) .................. 78 bmxpupba (program flash (pfm) user program base address) .................................................... 77 cm1con (comparator 1 control) ............................ 212 cmstat (comparator control register) .................. 213 cnconx (change notice control for portx) ......... 150 ctmucon (ctmu control) ..................................... 218 cvrcon (comparator voltage reference control). 216 dchxcon (dma channel x control) ....................... 111 dchxcptr (dma channel x cell pointer)............... 118 dchxcsiz (dma channel x cell-size) .................... 118 dchxdat (dma channel x pattern data) ............... 119 dchxdptr (channel x destination pointer)............ 117 dchxdsa (dma channel x destination start address) ................................................... 115 dchxdsiz (dma channel x destination size)......... 116 dchxecon (dma channel x event control)........... 112 dchxint (dma channel x interrupt control) ........... 113 dchxsptr (dma channel x source pointer).......... 117 dchxssa (dma channel x sour ce start address).. 115 dchxssiz (dma channel x source size) ............... 116 dcrccon (dma crc control) ............................... 108 dcrcdata (dma crc data) ................................. 110 dcrcxor (dma crcxor enable)........................ 110 devcfg0 (device configuration word 0................. 226 devcfg1 (device configuration word 1................. 228 devcfg2 (device configuration word 2................. 230 devcfg3 (device configuration word 3................. 232 devid (device and revision id) .............................. 234 dmaaddr (dma address) ...................................... 107 dmaaddr (dmr address)...................................... 107 dmacon (dma controller control) ......................... 106 dmastat (dma status) .......................................... 107 i2cxcon (i2c control)............................................. 175 i2cxstat (i2c status) ............................................. 177 icxcon (input capture x control)............................ 160 ifsx (interrupt flag status) ........................................ 92 intcon (interrupt control)......................................... 90 intstat (interrupt status)......................................... 91 ipcx (interrupt priority control) .................................. 93 nvmaddr (flash address) ....................................... 81 nvmcon (programming control) .............................. 80 nvmdata (flash program data)............................... 82 nvmkey (programming unlock)................................ 81 nvmsrcaddr (source data address) .................... 82 ocxcon (output compare x control) ..................... 164 osccon (oscillator control) ..................................... 97 pmaddr (parallel port address) ............................. 190 pmaen (parallel port pin enable)............................ 191 pmcon (parallel port control)................................. 186 pmmode (parallel port mode)................................. 188 pmstat (parallel port status (slave modes only).. 192 refocon (reference oscillator control) ............... 101 refotrim (reference oscillator trim)................... 103 rpnr (peripheral pin select output) ....................... 149 rswrst (software reset) ........................................ 85 rtccon (rtc control) ........................................... 194 rtcdate (rtc date value) ................................... 199 rtctime (rtc time value).................................... 198 spixcon (spi control) ............................................ 166 spixcon2 (spi control 2) ....................................... 169 spixstat (spi status)............................................. 170 t1con (type a timer control) ................................ 152 tptmr (temporal proximity timer)........................... 91 txcon (type b timer control) ................................ 157 u1addr (usb address) .......................................... 137 u1bdtp1 (usb bdt page 1) .................................. 139 u1bdtp2 (usb bdt page 2) .................................. 140 u1bdtp3 (usb bdt page 3) .................................. 140 u1cnfg1 (usb configuration 1)............................. 141 u1con (usb control).............................................. 135 u1eie (usb error interrupt enable) ......................... 133 u1eir (usb error interrupt status).......................... 131 u1ep0-u1ep15 (usb endpoint control) ................. 142 u1frmh (usb frame number high) ...................... 138 u1frml (usb frame number low)........................ 137 u1ie (usb interrupt enable) .................................... 130 u1ir (usb interrupt) ................................................ 128 u1otgcon (usb otg control) ............................. 126 u1otgie (usb otg interrupt enable).................... 124 u1otgir (usb otg interrupt status)..................... 123 u1otgstat (usb otg status) ............................. 125 u1pwrc (usb power control)................................ 127 u1sof (usb sof threshold).................................. 139 u1stat (usb status) .............................................. 134 u1tok (usb token) ................................................ 138 wdtcon (watchdog timer control) ....................... 236 resets................................................................................. 83 revision history................................................................ 307 www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 313 pic32mx1xx/2xx rtcalrm (rtc alarm control) .................................... 196 s serial peripheral interface (spi) ....................................... 165 software simulator (mplab sim)..................................... 243 special features ............................................................... 225 t timer1 module .................................................................. 151 timer2/3, timer4/5 modules ............................................. 155 timing diagrams 10-bit analog-to-digital conversion (asam = 0, ssrc<2:0> = 000) ........................ 278 10-bit analog-to-digital c onversion (chps<1:0> = 01, asam = 1, ssrc<2:0> = 111, samc<4:0> = 00001)............................................................... 279 ejtag ...................................................................... 284 external clock........................................................... 254 i/o characteristics .................................................... 257 i2cx bus data (master mode) .................................. 268 i2cx bus data (slave mode) .................................... 271 i2cx bus start/stop bits (master mode) ................... 268 i2cx bus start/stop bits (slave mode) ..................... 271 input capture (capx)................................................ 261 ocx/pwm ................................................................. 262 output compare (ocx)............................................. 262 parallel master port read......................................... 280 parallel master port write ......................................... 281 parallel slave port .................................................... 279 spix master mode (cke = 0) ................................... 263 spix master mode (cke = 1) ................................... 264 spix slave mode (cke = 0) ..................................... 265 spix slave mode (cke = 1) ..................................... 266 timer1, 2, 3, 4, 5 external clock............................... 260 uart reception ....................................................... 184 uart transmission (8-bit or 9-bit data)................... 184 timing requirements clko and i/o ........................................................... 257 timing specifications i2cx bus data requirements (master mode) ........... 269 i2cx bus data requirements (slave mode) ............. 272 input capture requirements..................................... 261 output compare requirements ................................ 262 simple ocx/pwm mode requirements.................... 262 spix master mode (cke = 0) requirements ............ 263 spix master mode (cke = 1) requirements ............ 264 spix slave mode (cke = 1) requirements .............. 266 spix slave mode requirements (cke = 0) .............. 265 u uart ................................................................................ 179 usb on-the-go (otg) .................................................... 121 v v cap pin ............................................................................ 237 voltage regulator (on-chip) ............................................ 237 w watchdog timer (wdt) .................................................... 235 www address.................................................................. 315 www, on-line support ..................................................... 16 www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 314 preliminary ? 2011-2012 microchip technology inc. notes: www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 315 pic32mx1xx/2xx the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faqs), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or de velopment tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sa les offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 316 preliminary ? 2011-2012 microchip technology inc. reader response it is our intention to provide you with the best document ation possible to ensure succe ssful use of your microchip product. if you wish to provide your comments on organiz ation, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outli ne to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds61168d pic32mx1xx/2xx 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you th ink would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 317 pic32mx1xx/2xx product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . architecture mx = m4k ? mcu core product groups 1xx = general purpose microcontroller family 2xx = general purpose microcontroller family flash memory family f = flash program memory program memory size 016 = 16k 032 = 32k pin count b = 28-pin c= 36-pin d= 44-pin temperature range i = -40c to +85c (industrial) v = -40c to +105c (v-temp) package ml = 28-lead (6x6 mm) qfn (plastic quad flatpack) ml = 44-lead (8x8 mm) qfn (plastic quad flatpack) pt = 44-lead (10x10x1 mm) tqfp (plastic thin quad flatpack) so = 28-lead (7.50 mm) soic (plastic small outline) sp = 28-lead (300 mil) spdip (skinny plastic dual in-line) ss = 28-lead (5.30 mm) ssop (plastic shrink small outline) tl = 36-lead (5x5 mm) vtla (very thin leadless array) tl = 44-lead (6x6 mm) vtla (very thin leadless array) pattern three-digit qtp, sqtp, code or special requirements (blank otherwise) es = engineering sample example: pic32mx110f032dt-i/pt: general purpose pic32, 32-bit risc mcu with m4k ? core, 32 kb program memory, 44-pin, industrial temperature, tqfp package. microchip brand architecture flash memory family pin count product groups program memory size (kb) pic32 m x 1x x f 032 d t - i / pt - xxx flash memory family pattern package temperature range tape and reel flag (if applicable) www.datasheet.co.kr datasheet pdf - http://www..net/
pic32mx1xx/2xx ds61168d-page 318 preliminary ? 2011-2012 microchip technology inc. notes: www.datasheet.co.kr datasheet pdf - http://www..net/
? 2011-2012 microchip technology inc. preliminary ds61168d-page 319 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, th e microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are register ed trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, application maestro, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2011-2012, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-62076-071-0 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality ? management ? ? ? ? by ? dnv ? == iso/ts ? 16949 ? == ? www.datasheet.co.kr datasheet pdf - http://www..net/
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